Overall: 3942/6810 fields covered

ADC1

0x40012000: Analog-to-digital converter

78/78 fields covered. Toggle Registers.

SR

status register

Offset: 0x0, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVR
rw
STRT
rw
JSTRT
rw
JEOC
rw
EOC
rw
AWD
rw
Toggle Fields.

AWD

Bit 0: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: Regular channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JEOC

Bit 2: Injected channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JSTRT

Bit 3: Injected channel start flag.

Allowed values:
0: NotStarted: No injected channel conversion started
1: Started: Injected channel conversion has started

STRT

Bit 4: Regular channel start flag.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

OVR

Bit 5: Overrun.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

CR1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OVRIE
rw
RES
rw
AWDEN
rw
JAWDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISCNUM
rw
JDISCEN
rw
DISCEN
rw
JAUTO
rw
AWDSGL
rw
SCAN
rw
JEOCIE
rw
AWDIE
rw
EOCIE
rw
AWDCH
rw
Toggle Fields.

AWDCH

Bits 0-4: Analog watchdog channel select bits.

Allowed values: 0-18

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled

AWDIE

Bit 6: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analogue watchdog interrupt disabled
1: Enabled: Analogue watchdog interrupt enabled

JEOCIE

Bit 7: Interrupt enable for injected channels.

Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled

SCAN

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

AWDSGL

Bit 9: Enable the watchdog on a single channel in scan mode.

Allowed values:
0: AllChannels: Analog watchdog enabled on all channels
1: SingleChannel: Analog watchdog enabled on a single channel

JAUTO

Bit 10: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

DISCEN

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

JDISCEN

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

DISCNUM

Bits 13-15: Discontinuous mode channel count.

Allowed values: 0-7

JAWDEN

Bit 22: Analog watchdog enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels

AWDEN

Bit 23: Analog watchdog enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

RES

Bits 24-25: Resolution.

Allowed values:
0: TwelveBit: 12-bit (15 ADCCLK cycles)
1: TenBit: 10-bit (13 ADCCLK cycles)
2: EightBit: 8-bit (11 ADCCLK cycles)
3: SixBit: 6-bit (9 ADCCLK cycles)

OVRIE

Bit 26: Overrun interrupt enable.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

CR2

control register 2

Offset: 0x8, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWSTART
rw
EXTEN
rw
EXTSEL
rw
JSWSTART
rw
JEXTEN
rw
JEXTSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALIGN
rw
EOCS
rw
DDS
rw
DMA
rw
CONT
rw
ADON
rw
Toggle Fields.

ADON

Bit 0: A/D Converter ON / OFF.

Allowed values:
0: Disabled: Disable ADC conversion and go to power down mode
1: Enabled: Enable ADC

CONT

Bit 1: Continuous conversion.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

DMA

Bit 8: Direct memory access mode (for single ADC mode).

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

DDS

Bit 9: DMA disable selection (for single ADC mode).

Allowed values:
0: Single: No new DMA request is issued after the last transfer
1: Continuous: DMA requests are issued as long as data are converted and DMA=1

EOCS

Bit 10: End of conversion selection.

Allowed values:
0: EachSequence: The EOC bit is set at the end of each sequence of regular conversions
1: EachConversion: The EOC bit is set at the end of each regular conversion

ALIGN

Bit 11: Data alignment.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

JEXTSEL

Bits 16-19: External event select for injected group.

Allowed values:
0: TIM1TRGO: Timer 1 TRGO event
1: TIM1CC4: Timer 1 CC4 event
2: TIM2TRGO: Timer 2 TRGO event
3: TIM2CC1: Timer 2 CC1 event
4: TIM3CC4: Timer 3 CC4 event
5: TIM4TRGO: Timer 4 TRGO event
7: TIM8CC4: Timer 8 CC4 event
8: TIM1TRGO2: Timer 1 TRGO(2) event
9: TIM8TRGO: Timer 8 TRGO event
10: TIM8TRGO2: Timer 8 TRGO(2) event
11: TIM3CC3: Timer 3 CC3 event
12: TIM5TRGO: Timer 5 TRGO event
13: TIM3CC1: Timer 3 CC1 event
14: TIM6TRGO: Timer 6 TRGO event

JEXTEN

Bits 20-21: External trigger enable for injected channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

JSWSTART

Bit 22: Start conversion of injected channels.

Allowed values:
1: Start: Starts conversion of injected channels

EXTSEL

Bits 24-27: External event select for regular group.

Allowed values:
0: TIM1CC1: Timer 1 CC1 event
1: TIM1CC2: Timer 1 CC2 event
2: TIM1CC3: Timer 1 CC3 event
3: TIM2CC2: Timer 2 CC2 event
4: TIM2CC3: Timer 2 CC3 event
5: TIM2CC4: Timer 2 CC4 event
6: TIM2TRGO: Timer 2 TRGO event

EXTEN

Bits 28-29: External trigger enable for regular channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

SWSTART

Bit 30: Start conversion of regular channels.

Allowed values:
1: Start: Starts conversion of regular channels

SMPR1

sample time register 1

Offset: 0xC, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP18
rw
SMP17
rw
SMP16
rw
SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw
SMP14
rw
SMP13
rw
SMP12
rw
SMP11
rw
SMP10
rw
Toggle Fields.

SMP10

Bits 0-2: Channel 10 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP11

Bits 3-5: Channel 11 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP12

Bits 6-8: Channel 12 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP13

Bits 9-11: Channel 13 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP14

Bits 12-14: Channel 14 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP15

Bits 15-17: Channel 15 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP16

Bits 18-20: Channel 16 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP17

Bits 21-23: Channel 17 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP18

Bits 24-26: Channel 18 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMPR2

sample time register 2

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw
SMP8
rw
SMP7
rw
SMP6
rw
SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw
SMP4
rw
SMP3
rw
SMP2
rw
SMP1
rw
SMP0
rw
Toggle Fields.

SMP0

Bits 0-2: Channel 0 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP1

Bits 3-5: Channel 1 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP2

Bits 6-8: Channel 2 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP3

Bits 9-11: Channel 3 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP4

Bits 12-14: Channel 4 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP5

Bits 15-17: Channel 5 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP6

Bits 18-20: Channel 6 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP7

Bits 21-23: Channel 7 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP8

Bits 24-26: Channel 8 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP9

Bits 27-29: Channel 9 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

JOFR%s

injected channel data offset register x

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields.

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0-4095

HTR

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HT
rw
Toggle Fields.

HT

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0-4095

LTR

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
rw
Toggle Fields.

LT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0-4095

SQR1

regular sequence register 1

Offset: 0x2C, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L
rw
SQ16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw
SQ15
rw
SQ14
rw
SQ13
rw
Toggle Fields.

SQ13

Bits 0-4: 13th conversion in regular sequence.

Allowed values: 0-18

SQ14

Bits 5-9: 14th conversion in regular sequence.

Allowed values: 0-18

SQ15

Bits 10-14: 15th conversion in regular sequence.

Allowed values: 0-18

SQ16

Bits 15-19: 16th conversion in regular sequence.

Allowed values: 0-18

L

Bits 20-23: Regular channel sequence length.

Allowed values: 0-15

SQR2

regular sequence register 2

Offset: 0x30, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ12
rw
SQ11
rw
SQ10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ10
rw
SQ9
rw
SQ8
rw
SQ7
rw
Toggle Fields.

SQ7

Bits 0-4: 7th conversion in regular sequence.

Allowed values: 0-18

SQ8

Bits 5-9: 8th conversion in regular sequence.

Allowed values: 0-18

SQ9

Bits 10-14: 9th conversion in regular sequence.

Allowed values: 0-18

SQ10

Bits 15-19: 10th conversion in regular sequence.

Allowed values: 0-18

SQ11

Bits 20-24: 11th conversion in regular sequence.

Allowed values: 0-18

SQ12

Bits 25-29: 12th conversion in regular sequence.

Allowed values: 0-18

SQR3

regular sequence register 3

Offset: 0x34, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ6
rw
SQ5
rw
SQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ4
rw
SQ3
rw
SQ2
rw
SQ1
rw
Toggle Fields.

SQ1

Bits 0-4: 1st conversion in regular sequence.

Allowed values: 0-18

SQ2

Bits 5-9: 2nd conversion in regular sequence.

Allowed values: 0-18

SQ3

Bits 10-14: 3rd conversion in regular sequence.

Allowed values: 0-18

SQ4

Bits 15-19: 4th conversion in regular sequence.

Allowed values: 0-18

SQ5

Bits 20-24: 5th conversion in regular sequence.

Allowed values: 0-18

SQ6

Bits 25-29: 6th conversion in regular sequence.

Allowed values: 0-18

JSQR

injected sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JL
rw
JSQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ4
rw
JSQ3
rw
JSQ2
rw
JSQ1
rw
Toggle Fields.

JSQ1

Bits 0-4: 1st conversion in injected sequence.

Allowed values: 0-18

JSQ2

Bits 5-9: 2nd conversion in injected sequence.

Allowed values: 0-18

JSQ3

Bits 10-14: 3rd conversion in injected sequence.

Allowed values: 0-18

JSQ4

Bits 15-19: 4th conversion in injected sequence.

Allowed values: 0-18

JL

Bits 20-21: Injected sequence length.

Allowed values: 0-3

JDR%s

injected data register x

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields.

JDATA

Bits 0-15: Injected data.

DR

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields.

DATA

Bits 0-15: Regular data.

ADC2

0x40012100: Analog-to-digital converter

78/78 fields covered. Toggle Registers.

SR

status register

Offset: 0x0, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVR
rw
STRT
rw
JSTRT
rw
JEOC
rw
EOC
rw
AWD
rw
Toggle Fields.

AWD

Bit 0: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: Regular channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JEOC

Bit 2: Injected channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JSTRT

Bit 3: Injected channel start flag.

Allowed values:
0: NotStarted: No injected channel conversion started
1: Started: Injected channel conversion has started

STRT

Bit 4: Regular channel start flag.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

OVR

Bit 5: Overrun.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

CR1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OVRIE
rw
RES
rw
AWDEN
rw
JAWDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISCNUM
rw
JDISCEN
rw
DISCEN
rw
JAUTO
rw
AWDSGL
rw
SCAN
rw
JEOCIE
rw
AWDIE
rw
EOCIE
rw
AWDCH
rw
Toggle Fields.

AWDCH

Bits 0-4: Analog watchdog channel select bits.

Allowed values: 0-18

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled

AWDIE

Bit 6: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analogue watchdog interrupt disabled
1: Enabled: Analogue watchdog interrupt enabled

JEOCIE

Bit 7: Interrupt enable for injected channels.

Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled

SCAN

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

AWDSGL

Bit 9: Enable the watchdog on a single channel in scan mode.

Allowed values:
0: AllChannels: Analog watchdog enabled on all channels
1: SingleChannel: Analog watchdog enabled on a single channel

JAUTO

Bit 10: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

DISCEN

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

JDISCEN

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

DISCNUM

Bits 13-15: Discontinuous mode channel count.

Allowed values: 0-7

JAWDEN

Bit 22: Analog watchdog enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels

AWDEN

Bit 23: Analog watchdog enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

RES

Bits 24-25: Resolution.

Allowed values:
0: TwelveBit: 12-bit (15 ADCCLK cycles)
1: TenBit: 10-bit (13 ADCCLK cycles)
2: EightBit: 8-bit (11 ADCCLK cycles)
3: SixBit: 6-bit (9 ADCCLK cycles)

OVRIE

Bit 26: Overrun interrupt enable.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

CR2

control register 2

Offset: 0x8, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWSTART
rw
EXTEN
rw
EXTSEL
rw
JSWSTART
rw
JEXTEN
rw
JEXTSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALIGN
rw
EOCS
rw
DDS
rw
DMA
rw
CONT
rw
ADON
rw
Toggle Fields.

ADON

Bit 0: A/D Converter ON / OFF.

Allowed values:
0: Disabled: Disable ADC conversion and go to power down mode
1: Enabled: Enable ADC

CONT

Bit 1: Continuous conversion.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

DMA

Bit 8: Direct memory access mode (for single ADC mode).

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

DDS

Bit 9: DMA disable selection (for single ADC mode).

Allowed values:
0: Single: No new DMA request is issued after the last transfer
1: Continuous: DMA requests are issued as long as data are converted and DMA=1

EOCS

Bit 10: End of conversion selection.

Allowed values:
0: EachSequence: The EOC bit is set at the end of each sequence of regular conversions
1: EachConversion: The EOC bit is set at the end of each regular conversion

ALIGN

Bit 11: Data alignment.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

JEXTSEL

Bits 16-19: External event select for injected group.

Allowed values:
0: TIM1TRGO: Timer 1 TRGO event
1: TIM1CC4: Timer 1 CC4 event
2: TIM2TRGO: Timer 2 TRGO event
3: TIM2CC1: Timer 2 CC1 event
4: TIM3CC4: Timer 3 CC4 event
5: TIM4TRGO: Timer 4 TRGO event
7: TIM8CC4: Timer 8 CC4 event
8: TIM1TRGO2: Timer 1 TRGO(2) event
9: TIM8TRGO: Timer 8 TRGO event
10: TIM8TRGO2: Timer 8 TRGO(2) event
11: TIM3CC3: Timer 3 CC3 event
12: TIM5TRGO: Timer 5 TRGO event
13: TIM3CC1: Timer 3 CC1 event
14: TIM6TRGO: Timer 6 TRGO event

JEXTEN

Bits 20-21: External trigger enable for injected channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

JSWSTART

Bit 22: Start conversion of injected channels.

Allowed values:
1: Start: Starts conversion of injected channels

EXTSEL

Bits 24-27: External event select for regular group.

Allowed values:
0: TIM1CC1: Timer 1 CC1 event
1: TIM1CC2: Timer 1 CC2 event
2: TIM1CC3: Timer 1 CC3 event
3: TIM2CC2: Timer 2 CC2 event
4: TIM2CC3: Timer 2 CC3 event
5: TIM2CC4: Timer 2 CC4 event
6: TIM2TRGO: Timer 2 TRGO event

EXTEN

Bits 28-29: External trigger enable for regular channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

SWSTART

Bit 30: Start conversion of regular channels.

Allowed values:
1: Start: Starts conversion of regular channels

SMPR1

sample time register 1

Offset: 0xC, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP18
rw
SMP17
rw
SMP16
rw
SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw
SMP14
rw
SMP13
rw
SMP12
rw
SMP11
rw
SMP10
rw
Toggle Fields.

SMP10

Bits 0-2: Channel 10 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP11

Bits 3-5: Channel 11 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP12

Bits 6-8: Channel 12 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP13

Bits 9-11: Channel 13 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP14

Bits 12-14: Channel 14 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP15

Bits 15-17: Channel 15 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP16

Bits 18-20: Channel 16 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP17

Bits 21-23: Channel 17 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP18

Bits 24-26: Channel 18 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMPR2

sample time register 2

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw
SMP8
rw
SMP7
rw
SMP6
rw
SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw
SMP4
rw
SMP3
rw
SMP2
rw
SMP1
rw
SMP0
rw
Toggle Fields.

SMP0

Bits 0-2: Channel 0 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP1

Bits 3-5: Channel 1 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP2

Bits 6-8: Channel 2 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP3

Bits 9-11: Channel 3 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP4

Bits 12-14: Channel 4 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP5

Bits 15-17: Channel 5 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP6

Bits 18-20: Channel 6 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP7

Bits 21-23: Channel 7 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP8

Bits 24-26: Channel 8 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP9

Bits 27-29: Channel 9 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

JOFR%s

injected channel data offset register x

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields.

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0-4095

HTR

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HT
rw
Toggle Fields.

HT

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0-4095

LTR

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
rw
Toggle Fields.

LT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0-4095

SQR1

regular sequence register 1

Offset: 0x2C, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L
rw
SQ16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw
SQ15
rw
SQ14
rw
SQ13
rw
Toggle Fields.

SQ13

Bits 0-4: 13th conversion in regular sequence.

Allowed values: 0-18

SQ14

Bits 5-9: 14th conversion in regular sequence.

Allowed values: 0-18

SQ15

Bits 10-14: 15th conversion in regular sequence.

Allowed values: 0-18

SQ16

Bits 15-19: 16th conversion in regular sequence.

Allowed values: 0-18

L

Bits 20-23: Regular channel sequence length.

Allowed values: 0-15

SQR2

regular sequence register 2

Offset: 0x30, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ12
rw
SQ11
rw
SQ10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ10
rw
SQ9
rw
SQ8
rw
SQ7
rw
Toggle Fields.

SQ7

Bits 0-4: 7th conversion in regular sequence.

Allowed values: 0-18

SQ8

Bits 5-9: 8th conversion in regular sequence.

Allowed values: 0-18

SQ9

Bits 10-14: 9th conversion in regular sequence.

Allowed values: 0-18

SQ10

Bits 15-19: 10th conversion in regular sequence.

Allowed values: 0-18

SQ11

Bits 20-24: 11th conversion in regular sequence.

Allowed values: 0-18

SQ12

Bits 25-29: 12th conversion in regular sequence.

Allowed values: 0-18

SQR3

regular sequence register 3

Offset: 0x34, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ6
rw
SQ5
rw
SQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ4
rw
SQ3
rw
SQ2
rw
SQ1
rw
Toggle Fields.

SQ1

Bits 0-4: 1st conversion in regular sequence.

Allowed values: 0-18

SQ2

Bits 5-9: 2nd conversion in regular sequence.

Allowed values: 0-18

SQ3

Bits 10-14: 3rd conversion in regular sequence.

Allowed values: 0-18

SQ4

Bits 15-19: 4th conversion in regular sequence.

Allowed values: 0-18

SQ5

Bits 20-24: 5th conversion in regular sequence.

Allowed values: 0-18

SQ6

Bits 25-29: 6th conversion in regular sequence.

Allowed values: 0-18

JSQR

injected sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JL
rw
JSQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ4
rw
JSQ3
rw
JSQ2
rw
JSQ1
rw
Toggle Fields.

JSQ1

Bits 0-4: 1st conversion in injected sequence.

Allowed values: 0-18

JSQ2

Bits 5-9: 2nd conversion in injected sequence.

Allowed values: 0-18

JSQ3

Bits 10-14: 3rd conversion in injected sequence.

Allowed values: 0-18

JSQ4

Bits 15-19: 4th conversion in injected sequence.

Allowed values: 0-18

JL

Bits 20-21: Injected sequence length.

Allowed values: 0-3

JDR%s

injected data register x

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields.

JDATA

Bits 0-15: Injected data.

DR

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields.

DATA

Bits 0-15: Regular data.

ADC3

0x40012200: Analog-to-digital converter

78/78 fields covered. Toggle Registers.

SR

status register

Offset: 0x0, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVR
rw
STRT
rw
JSTRT
rw
JEOC
rw
EOC
rw
AWD
rw
Toggle Fields.

AWD

Bit 0: Analog watchdog flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: Regular channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JEOC

Bit 2: Injected channel end of conversion.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JSTRT

Bit 3: Injected channel start flag.

Allowed values:
0: NotStarted: No injected channel conversion started
1: Started: Injected channel conversion has started

STRT

Bit 4: Regular channel start flag.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

OVR

Bit 5: Overrun.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

CR1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OVRIE
rw
RES
rw
AWDEN
rw
JAWDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISCNUM
rw
JDISCEN
rw
DISCEN
rw
JAUTO
rw
AWDSGL
rw
SCAN
rw
JEOCIE
rw
AWDIE
rw
EOCIE
rw
AWDCH
rw
Toggle Fields.

AWDCH

Bits 0-4: Analog watchdog channel select bits.

Allowed values: 0-18

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled

AWDIE

Bit 6: Analog watchdog interrupt enable.

Allowed values:
0: Disabled: Analogue watchdog interrupt disabled
1: Enabled: Analogue watchdog interrupt enabled

JEOCIE

Bit 7: Interrupt enable for injected channels.

Allowed values:
0: Disabled: JEOC interrupt disabled
1: Enabled: JEOC interrupt enabled

SCAN

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

AWDSGL

Bit 9: Enable the watchdog on a single channel in scan mode.

Allowed values:
0: AllChannels: Analog watchdog enabled on all channels
1: SingleChannel: Analog watchdog enabled on a single channel

JAUTO

Bit 10: Automatic injected group conversion.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

DISCEN

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

JDISCEN

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

DISCNUM

Bits 13-15: Discontinuous mode channel count.

Allowed values: 0-7

JAWDEN

Bit 22: Analog watchdog enable on injected channels.

Allowed values:
0: Disabled: Analog watchdog disabled on injected channels
1: Enabled: Analog watchdog enabled on injected channels

AWDEN

Bit 23: Analog watchdog enable on regular channels.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

RES

Bits 24-25: Resolution.

Allowed values:
0: TwelveBit: 12-bit (15 ADCCLK cycles)
1: TenBit: 10-bit (13 ADCCLK cycles)
2: EightBit: 8-bit (11 ADCCLK cycles)
3: SixBit: 6-bit (9 ADCCLK cycles)

OVRIE

Bit 26: Overrun interrupt enable.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

CR2

control register 2

Offset: 0x8, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWSTART
rw
EXTEN
rw
EXTSEL
rw
JSWSTART
rw
JEXTEN
rw
JEXTSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALIGN
rw
EOCS
rw
DDS
rw
DMA
rw
CONT
rw
ADON
rw
Toggle Fields.

ADON

Bit 0: A/D Converter ON / OFF.

Allowed values:
0: Disabled: Disable ADC conversion and go to power down mode
1: Enabled: Enable ADC

CONT

Bit 1: Continuous conversion.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

DMA

Bit 8: Direct memory access mode (for single ADC mode).

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

DDS

Bit 9: DMA disable selection (for single ADC mode).

Allowed values:
0: Single: No new DMA request is issued after the last transfer
1: Continuous: DMA requests are issued as long as data are converted and DMA=1

EOCS

Bit 10: End of conversion selection.

Allowed values:
0: EachSequence: The EOC bit is set at the end of each sequence of regular conversions
1: EachConversion: The EOC bit is set at the end of each regular conversion

ALIGN

Bit 11: Data alignment.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

JEXTSEL

Bits 16-19: External event select for injected group.

Allowed values:
0: TIM1TRGO: Timer 1 TRGO event
1: TIM1CC4: Timer 1 CC4 event
2: TIM2TRGO: Timer 2 TRGO event
3: TIM2CC1: Timer 2 CC1 event
4: TIM3CC4: Timer 3 CC4 event
5: TIM4TRGO: Timer 4 TRGO event
7: TIM8CC4: Timer 8 CC4 event
8: TIM1TRGO2: Timer 1 TRGO(2) event
9: TIM8TRGO: Timer 8 TRGO event
10: TIM8TRGO2: Timer 8 TRGO(2) event
11: TIM3CC3: Timer 3 CC3 event
12: TIM5TRGO: Timer 5 TRGO event
13: TIM3CC1: Timer 3 CC1 event
14: TIM6TRGO: Timer 6 TRGO event

JEXTEN

Bits 20-21: External trigger enable for injected channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

JSWSTART

Bit 22: Start conversion of injected channels.

Allowed values:
1: Start: Starts conversion of injected channels

EXTSEL

Bits 24-27: External event select for regular group.

Allowed values:
0: TIM1CC1: Timer 1 CC1 event
1: TIM1CC2: Timer 1 CC2 event
2: TIM1CC3: Timer 1 CC3 event
3: TIM2CC2: Timer 2 CC2 event
4: TIM2CC3: Timer 2 CC3 event
5: TIM2CC4: Timer 2 CC4 event
6: TIM2TRGO: Timer 2 TRGO event

EXTEN

Bits 28-29: External trigger enable for regular channels.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

SWSTART

Bit 30: Start conversion of regular channels.

Allowed values:
1: Start: Starts conversion of regular channels

SMPR1

sample time register 1

Offset: 0xC, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP18
rw
SMP17
rw
SMP16
rw
SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw
SMP14
rw
SMP13
rw
SMP12
rw
SMP11
rw
SMP10
rw
Toggle Fields.

SMP10

Bits 0-2: Channel 10 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP11

Bits 3-5: Channel 11 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP12

Bits 6-8: Channel 12 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP13

Bits 9-11: Channel 13 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP14

Bits 12-14: Channel 14 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP15

Bits 15-17: Channel 15 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP16

Bits 18-20: Channel 16 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP17

Bits 21-23: Channel 17 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP18

Bits 24-26: Channel 18 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMPR2

sample time register 2

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw
SMP8
rw
SMP7
rw
SMP6
rw
SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw
SMP4
rw
SMP3
rw
SMP2
rw
SMP1
rw
SMP0
rw
Toggle Fields.

SMP0

Bits 0-2: Channel 0 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP1

Bits 3-5: Channel 1 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP2

Bits 6-8: Channel 2 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP3

Bits 9-11: Channel 3 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP4

Bits 12-14: Channel 4 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP5

Bits 15-17: Channel 5 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP6

Bits 18-20: Channel 6 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP7

Bits 21-23: Channel 7 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP8

Bits 24-26: Channel 8 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

SMP9

Bits 27-29: Channel 9 sampling time selection.

Allowed values:
0: Cycles3: 3 cycles
1: Cycles15: 15 cycles
2: Cycles28: 28 cycles
3: Cycles56: 56 cycles
4: Cycles84: 84 cycles
5: Cycles112: 112 cycles
6: Cycles144: 144 cycles
7: Cycles480: 480 cycles

JOFR%s

injected channel data offset register x

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JOFFSET
rw
Toggle Fields.

JOFFSET

Bits 0-11: Data offset for injected channel x.

Allowed values: 0-4095

HTR

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HT
rw
Toggle Fields.

HT

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0-4095

LTR

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
rw
Toggle Fields.

LT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0-4095

SQR1

regular sequence register 1

Offset: 0x2C, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L
rw
SQ16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw
SQ15
rw
SQ14
rw
SQ13
rw
Toggle Fields.

SQ13

Bits 0-4: 13th conversion in regular sequence.

Allowed values: 0-18

SQ14

Bits 5-9: 14th conversion in regular sequence.

Allowed values: 0-18

SQ15

Bits 10-14: 15th conversion in regular sequence.

Allowed values: 0-18

SQ16

Bits 15-19: 16th conversion in regular sequence.

Allowed values: 0-18

L

Bits 20-23: Regular channel sequence length.

Allowed values: 0-15

SQR2

regular sequence register 2

Offset: 0x30, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ12
rw
SQ11
rw
SQ10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ10
rw
SQ9
rw
SQ8
rw
SQ7
rw
Toggle Fields.

SQ7

Bits 0-4: 7th conversion in regular sequence.

Allowed values: 0-18

SQ8

Bits 5-9: 8th conversion in regular sequence.

Allowed values: 0-18

SQ9

Bits 10-14: 9th conversion in regular sequence.

Allowed values: 0-18

SQ10

Bits 15-19: 10th conversion in regular sequence.

Allowed values: 0-18

SQ11

Bits 20-24: 11th conversion in regular sequence.

Allowed values: 0-18

SQ12

Bits 25-29: 12th conversion in regular sequence.

Allowed values: 0-18

SQR3

regular sequence register 3

Offset: 0x34, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ6
rw
SQ5
rw
SQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ4
rw
SQ3
rw
SQ2
rw
SQ1
rw
Toggle Fields.

SQ1

Bits 0-4: 1st conversion in regular sequence.

Allowed values: 0-18

SQ2

Bits 5-9: 2nd conversion in regular sequence.

Allowed values: 0-18

SQ3

Bits 10-14: 3rd conversion in regular sequence.

Allowed values: 0-18

SQ4

Bits 15-19: 4th conversion in regular sequence.

Allowed values: 0-18

SQ5

Bits 20-24: 5th conversion in regular sequence.

Allowed values: 0-18

SQ6

Bits 25-29: 6th conversion in regular sequence.

Allowed values: 0-18

JSQR

injected sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JL
rw
JSQ4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ4
rw
JSQ3
rw
JSQ2
rw
JSQ1
rw
Toggle Fields.

JSQ1

Bits 0-4: 1st conversion in injected sequence.

Allowed values: 0-18

JSQ2

Bits 5-9: 2nd conversion in injected sequence.

Allowed values: 0-18

JSQ3

Bits 10-14: 3rd conversion in injected sequence.

Allowed values: 0-18

JSQ4

Bits 15-19: 4th conversion in injected sequence.

Allowed values: 0-18

JL

Bits 20-21: Injected sequence length.

Allowed values: 0-3

JDR%s

injected data register x

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle Fields.

JDATA

Bits 0-15: Injected data.

DR

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle Fields.

DATA

Bits 0-15: Regular data.

ADC_Common

0x40012300: Common ADC registers

27/27 fields covered. Toggle Registers.

CSR

ADC Common status register

Offset: 0x0, reset: 0x00000000, access: read-only

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OVR3
r
STRT3
r
JSTRT3
r
JEOC3
r
EOC3
r
AWD3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVR2
r
STRT2
r
JSTRT2
r
JEOC2
r
EOC2
r
AWD2
r
OVR1
r
STRT1
r
JSTRT1
r
JEOC1
r
EOC1
r
AWD1
r
Toggle Fields.

AWD1

Bit 0: Analog watchdog flag of ADC 1.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC1

Bit 1: End of conversion of ADC 1.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JEOC1

Bit 2: Injected channel end of conversion of ADC 1.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JSTRT1

Bit 3: Injected channel Start flag of ADC 1.

Allowed values:
0: NotStarted: No injected channel conversion started
1: Started: Injected channel conversion has started

STRT1

Bit 4: Regular channel Start flag of ADC 1.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

OVR1

Bit 5: Overrun flag of ADC 1.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

AWD2

Bit 8: Analog watchdog flag of ADC 2.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC2

Bit 9: End of conversion of ADC 2.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JEOC2

Bit 10: Injected channel end of conversion of ADC 2.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JSTRT2

Bit 11: Injected channel Start flag of ADC 2.

Allowed values:
0: NotStarted: No injected channel conversion started
1: Started: Injected channel conversion has started

STRT2

Bit 12: Regular channel Start flag of ADC 2.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

OVR2

Bit 13: Overrun flag of ADC 2.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

AWD3

Bit 16: Analog watchdog flag of ADC 3.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC3

Bit 17: End of conversion of ADC 3.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JEOC3

Bit 18: Injected channel end of conversion of ADC 3.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

JSTRT3

Bit 19: Injected channel Start flag of ADC 3.

Allowed values:
0: NotStarted: No injected channel conversion started
1: Started: Injected channel conversion has started

STRT3

Bit 20: Regular channel Start flag of ADC 3.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

OVR3

Bit 21: Overrun flag of ADC3.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

CCR

ADC common control register

Offset: 0x4, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSVREFE
rw
VBATE
rw
ADCPRE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA
rw
DDS
rw
DELAY
rw
MULTI
rw
Toggle Fields.

MULTI

Bits 0-4: Multi ADC mode selection.

Allowed values:
0: Independent: All the ADCs independent: independent mode
1: DualRJ: Dual ADC1 and ADC2, combined regular and injected simultaneous mode
2: DualRA: Dual ADC1 and ADC2, combined regular and alternate trigger mode
5: DualJ: Dual ADC1 and ADC2, injected simultaneous mode only
6: DualR: Dual ADC1 and ADC2, regular simultaneous mode only
7: DualI: Dual ADC1 and ADC2, interleaved mode only
9: DualA: Dual ADC1 and ADC2, alternate trigger mode only
17: TripleRJ: Triple ADC, regular and injected simultaneous mode
18: TripleRA: Triple ADC, regular and alternate trigger mode
21: TripleJ: Triple ADC, injected simultaneous mode only
22: TripleR: Triple ADC, regular simultaneous mode only
23: TripleI: Triple ADC, interleaved mode only
24: TripleA: Triple ADC, alternate trigger mode only

DELAY

Bits 8-11: Delay between 2 sampling phases.

Allowed values: 0-15

DDS

Bit 13: DMA disable selection for multi-ADC mode.

Allowed values:
0: Single: No new DMA request is issued after the last transfer
1: Continuous: DMA requests are issued as long as data are converted and DMA=01, 10 or 11

DMA

Bits 14-15: Direct memory access mode for multi ADC mode.

Allowed values:
0: Disabled: DMA mode disabled
1: Mode1: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)
2: Mode2: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
3: Mode3: DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)

ADCPRE

Bits 16-17: ADC prescaler.

Allowed values:
0: Div2: PCLK2 divided by 2
1: Div4: PCLK2 divided by 4
2: Div6: PCLK2 divided by 6
3: Div8: PCLK2 divided by 8

VBATE

Bit 22: VBAT enable.

Allowed values:
0: Disabled: V_BAT channel disabled
1: Enabled: V_BAT channel enabled

TSVREFE

Bit 23: Temperature sensor and VREFINT enable.

Allowed values:
0: Disabled: Temperature sensor and V_REFINT channel disabled
1: Enabled: Temperature sensor and V_REFINT channel enabled

CDR

ADC common regular data register for dual and triple modes

Offset: 0x8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA1
r
Toggle Fields.

DATA1

Bits 0-15: 1st data item of a pair of regular conversions.

DATA2

Bits 16-31: 2nd data item of a pair of regular conversions.

CAN1

0x40006400: Controller area network

57/218 fields covered. Toggle Registers.

MCR

master control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET
rw
TTCM
rw
ABOM
rw
AWUM
rw
NART
rw
RFLM
rw
TXFP
rw
SLEEP
rw
INRQ
rw
Toggle Fields.

INRQ

Bit 0: INRQ.

SLEEP

Bit 1: SLEEP.

TXFP

Bit 2: TXFP.

RFLM

Bit 3: RFLM.

NART

Bit 4: NART.

AWUM

Bit 5: AWUM.

ABOM

Bit 6: ABOM.

TTCM

Bit 7: TTCM.

RESET

Bit 15: RESET.

DBF

Bit 16: DBF.

MSR

master status register

Offset: 0x4, reset: 0x00000000, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX
r
SAMP
r
RXM
r
TXM
r
SLAKI
rw
WKUI
rw
ERRI
rw
SLAK
r
INAK
r
Toggle Fields.

INAK

Bit 0: INAK.

SLAK

Bit 1: SLAK.

ERRI

Bit 2: ERRI.

WKUI

Bit 3: WKUI.

SLAKI

Bit 4: SLAKI.

TXM

Bit 8: TXM.

RXM

Bit 9: RXM.

SAMP

Bit 10: SAMP.

RX

Bit 11: RX.

TSR

transmit status register

Offset: 0x8, reset: 0x00000000, access: Unspecified

7/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOW2
r
LOW1
r
LOW0
r
TME2
r
TME1
r
TME0
r
CODE
r
ABRQ2
rw
TERR2
rw
ALST2
rw
TXOK2
rw
RQCP2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRQ1
rw
TERR1
rw
ALST1
rw
TXOK1
rw
RQCP1
rw
ABRQ0
rw
TERR0
rw
ALST0
rw
TXOK0
rw
RQCP0
rw
Toggle Fields.

RQCP0

Bit 0: RQCP0.

TXOK0

Bit 1: TXOK0.

ALST0

Bit 2: ALST0.

TERR0

Bit 3: TERR0.

ABRQ0

Bit 7: ABRQ0.

RQCP1

Bit 8: RQCP1.

TXOK1

Bit 9: TXOK1.

ALST1

Bit 10: ALST1.

TERR1

Bit 11: TERR1.

ABRQ1

Bit 15: ABRQ1.

RQCP2

Bit 16: RQCP2.

TXOK2

Bit 17: TXOK2.

ALST2

Bit 18: ALST2.

TERR2

Bit 19: TERR2.

ABRQ2

Bit 23: ABRQ2.

CODE

Bits 24-25: CODE.

TME0

Bit 26: Lowest priority flag for mailbox 0.

TME1

Bit 27: Lowest priority flag for mailbox 1.

TME2

Bit 28: Lowest priority flag for mailbox 2.

LOW0

Bit 29: Lowest priority flag for mailbox 0.

LOW1

Bit 30: Lowest priority flag for mailbox 1.

LOW2

Bit 31: Lowest priority flag for mailbox 2.

RF%sR

receive FIFO 0 register

Offset: 0xC, reset: 0x00000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFOM
rw
FOVR
rw
FULL
rw
FMP
r
Toggle Fields.

FMP

Bits 0-1: FMP0.

FULL

Bit 3: FULL0.

Allowed values:
0: NotFull: FIFO x is not full
1: Full: FIFO x is full

FOVR

Bit 4: FOVR0.

Allowed values:
0: NoOverrun: No FIFO x overrun
1: Overrun: FIFO x overrun

RFOM

Bit 5: RFOM0.

Allowed values:
1: Release: Set by software to release the output mailbox of the FIFO

IER

interrupt enable register

Offset: 0x14, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLKIE
rw
WKUIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw
LECIE
rw
BOFIE
rw
EPVIE
rw
EWGIE
rw
FOVIE1
rw
FFIE1
rw
FMPIE1
rw
FOVIE0
rw
FFIE0
rw
FMPIE0
rw
TMEIE
rw
Toggle Fields.

TMEIE

Bit 0: TMEIE.

Allowed values:
0: Disabled: No interrupt when RQCPx bit is set
1: Enabled: Interrupt generated when RQCPx bit is set

FMPIE0

Bit 1: FMPIE0.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

FFIE0

Bit 2: FFIE0.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

FOVIE0

Bit 3: FOVIE0.

Allowed values:
0: Disabled: No interrupt when FOVR bit is set
1: Enabled: Interrupt generated when FOVR bit is set

FMPIE1

Bit 4: FMPIE1.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00b
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

FFIE1

Bit 5: FFIE1.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

FOVIE1

Bit 6: FOVIE1.

Allowed values:
0: Disabled: No interrupt when FOVR is set
1: Enabled: Interrupt generation when FOVR is set

EWGIE

Bit 8: EWGIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EWGF is set
1: Enabled: ERRI bit will be set when EWGF is set

EPVIE

Bit 9: EPVIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EPVF is set
1: Enabled: ERRI bit will be set when EPVF is set

BOFIE

Bit 10: BOFIE.

Allowed values:
0: Disabled: ERRI bit will not be set when BOFF is set
1: Enabled: ERRI bit will be set when BOFF is set

LECIE

Bit 11: LECIE.

Allowed values:
0: Disabled: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection
1: Enabled: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection

ERRIE

Bit 15: ERRIE.

Allowed values:
0: Disabled: No interrupt will be generated when an error condition is pending in the CAN_ESR
1: Enabled: An interrupt will be generation when an error condition is pending in the CAN_ESR

WKUIE

Bit 16: WKUIE.

Allowed values:
0: Disabled: No interrupt when WKUI is set
1: Enabled: Interrupt generated when WKUI bit is set

SLKIE

Bit 17: SLKIE.

Allowed values:
0: Disabled: No interrupt when SLAKI bit is set
1: Enabled: Interrupt generated when SLAKI bit is set

ESR

interrupt enable register

Offset: 0x18, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REC
r
TEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEC
rw
BOFF
r
EPVF
r
EWGF
r
Toggle Fields.

EWGF

Bit 0: EWGF.

EPVF

Bit 1: EPVF.

BOFF

Bit 2: BOFF.

LEC

Bits 4-6: LEC.

Allowed values:
0: NoError: No Error
1: Stuff: Stuff Error
2: Form: Form Error
3: Ack: Acknowledgment Error
4: BitRecessive: Bit recessive Error
5: BitDominant: Bit dominant Error
6: Crc: CRC Error
7: Custom: Set by software

TEC

Bits 16-23: TEC.

REC

Bits 24-31: REC.

BTR

bit timing register

Offset: 0x1C, reset: 0x00000000, access: read-write

2/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SILM
rw
LBKM
rw
SJW
rw
TS2
rw
TS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRP
rw
Toggle Fields.

BRP

Bits 0-9: BRP.

TS1

Bits 16-19: TS1.

TS2

Bits 20-22: TS2.

SJW

Bits 24-25: SJW.

LBKM

Bit 30: LBKM.

Allowed values:
0: Disabled: Loop Back Mode disabled
1: Enabled: Loop Back Mode enabled

SILM

Bit 31: SILM.

Allowed values:
0: Normal: Normal operation
1: Silent: Silent Mode

FMR

filter master register

Offset: 0x200, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAN2SB
rw
FINIT
rw
Toggle Fields.

FINIT

Bit 0: FINIT.

CAN2SB

Bits 8-13: CAN2SB.

FM1R

filter mode register

Offset: 0x204, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FBM27
rw
FBM26
rw
FBM25
rw
FBM24
rw
FBM23
rw
FBM22
rw
FBM21
rw
FBM20
rw
FBM19
rw
FBM18
rw
FBM17
rw
FBM16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FBM15
rw
FBM14
rw
FBM13
rw
FBM12
rw
FBM11
rw
FBM10
rw
FBM9
rw
FBM8
rw
FBM7
rw
FBM6
rw
FBM5
rw
FBM4
rw
FBM3
rw
FBM2
rw
FBM1
rw
FBM0
rw
Toggle Fields.

FBM0

Bit 0: Filter mode.

FBM1

Bit 1: Filter mode.

FBM2

Bit 2: Filter mode.

FBM3

Bit 3: Filter mode.

FBM4

Bit 4: Filter mode.

FBM5

Bit 5: Filter mode.

FBM6

Bit 6: Filter mode.

FBM7

Bit 7: Filter mode.

FBM8

Bit 8: Filter mode.

FBM9

Bit 9: Filter mode.

FBM10

Bit 10: Filter mode.

FBM11

Bit 11: Filter mode.

FBM12

Bit 12: Filter mode.

FBM13

Bit 13: Filter mode.

FBM14

Bit 14: Filter mode.

FBM15

Bit 15: Filter mode.

FBM16

Bit 16: Filter mode.

FBM17

Bit 17: Filter mode.

FBM18

Bit 18: Filter mode.

FBM19

Bit 19: Filter mode.

FBM20

Bit 20: Filter mode.

FBM21

Bit 21: Filter mode.

FBM22

Bit 22: Filter mode.

FBM23

Bit 23: Filter mode.

FBM24

Bit 24: Filter mode.

FBM25

Bit 25: Filter mode.

FBM26

Bit 26: Filter mode.

FBM27

Bit 27: Filter mode.

FS1R

filter scale register

Offset: 0x20C, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSC27
rw
FSC26
rw
FSC25
rw
FSC24
rw
FSC23
rw
FSC22
rw
FSC21
rw
FSC20
rw
FSC19
rw
FSC18
rw
FSC17
rw
FSC16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSC15
rw
FSC14
rw
FSC13
rw
FSC12
rw
FSC11
rw
FSC10
rw
FSC9
rw
FSC8
rw
FSC7
rw
FSC6
rw
FSC5
rw
FSC4
rw
FSC3
rw
FSC2
rw
FSC1
rw
FSC0
rw
Toggle Fields.

FSC0

Bit 0: Filter scale configuration.

FSC1

Bit 1: Filter scale configuration.

FSC2

Bit 2: Filter scale configuration.

FSC3

Bit 3: Filter scale configuration.

FSC4

Bit 4: Filter scale configuration.

FSC5

Bit 5: Filter scale configuration.

FSC6

Bit 6: Filter scale configuration.

FSC7

Bit 7: Filter scale configuration.

FSC8

Bit 8: Filter scale configuration.

FSC9

Bit 9: Filter scale configuration.

FSC10

Bit 10: Filter scale configuration.

FSC11

Bit 11: Filter scale configuration.

FSC12

Bit 12: Filter scale configuration.

FSC13

Bit 13: Filter scale configuration.

FSC14

Bit 14: Filter scale configuration.

FSC15

Bit 15: Filter scale configuration.

FSC16

Bit 16: Filter scale configuration.

FSC17

Bit 17: Filter scale configuration.

FSC18

Bit 18: Filter scale configuration.

FSC19

Bit 19: Filter scale configuration.

FSC20

Bit 20: Filter scale configuration.

FSC21

Bit 21: Filter scale configuration.

FSC22

Bit 22: Filter scale configuration.

FSC23

Bit 23: Filter scale configuration.

FSC24

Bit 24: Filter scale configuration.

FSC25

Bit 25: Filter scale configuration.

FSC26

Bit 26: Filter scale configuration.

FSC27

Bit 27: Filter scale configuration.

FFA1R

filter FIFO assignment register

Offset: 0x214, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FFA27
rw
FFA26
rw
FFA25
rw
FFA24
rw
FFA23
rw
FFA22
rw
FFA21
rw
FFA20
rw
FFA19
rw
FFA18
rw
FFA17
rw
FFA16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFA15
rw
FFA14
rw
FFA13
rw
FFA12
rw
FFA11
rw
FFA10
rw
FFA9
rw
FFA8
rw
FFA7
rw
FFA6
rw
FFA5
rw
FFA4
rw
FFA3
rw
FFA2
rw
FFA1
rw
FFA0
rw
Toggle Fields.

FFA0

Bit 0: Filter FIFO assignment for filter 0.

FFA1

Bit 1: Filter FIFO assignment for filter 1.

FFA2

Bit 2: Filter FIFO assignment for filter 2.

FFA3

Bit 3: Filter FIFO assignment for filter 3.

FFA4

Bit 4: Filter FIFO assignment for filter 4.

FFA5

Bit 5: Filter FIFO assignment for filter 5.

FFA6

Bit 6: Filter FIFO assignment for filter 6.

FFA7

Bit 7: Filter FIFO assignment for filter 7.

FFA8

Bit 8: Filter FIFO assignment for filter 8.

FFA9

Bit 9: Filter FIFO assignment for filter 9.

FFA10

Bit 10: Filter FIFO assignment for filter 10.

FFA11

Bit 11: Filter FIFO assignment for filter 11.

FFA12

Bit 12: Filter FIFO assignment for filter 12.

FFA13

Bit 13: Filter FIFO assignment for filter 13.

FFA14

Bit 14: Filter FIFO assignment for filter 14.

FFA15

Bit 15: Filter FIFO assignment for filter 15.

FFA16

Bit 16: Filter FIFO assignment for filter 16.

FFA17

Bit 17: Filter FIFO assignment for filter 17.

FFA18

Bit 18: Filter FIFO assignment for filter 18.

FFA19

Bit 19: Filter FIFO assignment for filter 19.

FFA20

Bit 20: Filter FIFO assignment for filter 20.

FFA21

Bit 21: Filter FIFO assignment for filter 21.

FFA22

Bit 22: Filter FIFO assignment for filter 22.

FFA23

Bit 23: Filter FIFO assignment for filter 23.

FFA24

Bit 24: Filter FIFO assignment for filter 24.

FFA25

Bit 25: Filter FIFO assignment for filter 25.

FFA26

Bit 26: Filter FIFO assignment for filter 26.

FFA27

Bit 27: Filter FIFO assignment for filter 27.

FA1R

filter activation register

Offset: 0x21C, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FACT27
rw
FACT26
rw
FACT25
rw
FACT24
rw
FACT23
rw
FACT22
rw
FACT21
rw
FACT20
rw
FACT19
rw
FACT18
rw
FACT17
rw
FACT16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FACT15
rw
FACT14
rw
FACT13
rw
FACT12
rw
FACT11
rw
FACT10
rw
FACT9
rw
FACT8
rw
FACT7
rw
FACT6
rw
FACT5
rw
FACT4
rw
FACT3
rw
FACT2
rw
FACT1
rw
FACT0
rw
Toggle Fields.

FACT0

Bit 0: Filter active.

FACT1

Bit 1: Filter active.

FACT2

Bit 2: Filter active.

FACT3

Bit 3: Filter active.

FACT4

Bit 4: Filter active.

FACT5

Bit 5: Filter active.

FACT6

Bit 6: Filter active.

FACT7

Bit 7: Filter active.

FACT8

Bit 8: Filter active.

FACT9

Bit 9: Filter active.

FACT10

Bit 10: Filter active.

FACT11

Bit 11: Filter active.

FACT12

Bit 12: Filter active.

FACT13

Bit 13: Filter active.

FACT14

Bit 14: Filter active.

FACT15

Bit 15: Filter active.

FACT16

Bit 16: Filter active.

FACT17

Bit 17: Filter active.

FACT18

Bit 18: Filter active.

FACT19

Bit 19: Filter active.

FACT20

Bit 20: Filter active.

FACT21

Bit 21: Filter active.

FACT22

Bit 22: Filter active.

FACT23

Bit 23: Filter active.

FACT24

Bit 24: Filter active.

FACT25

Bit 25: Filter active.

FACT26

Bit 26: Filter active.

FACT27

Bit 27: Filter active.

CAN2

0x40006800: Controller area network

57/218 fields covered. Toggle Registers.

MCR

master control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET
rw
TTCM
rw
ABOM
rw
AWUM
rw
NART
rw
RFLM
rw
TXFP
rw
SLEEP
rw
INRQ
rw
Toggle Fields.

INRQ

Bit 0: INRQ.

SLEEP

Bit 1: SLEEP.

TXFP

Bit 2: TXFP.

RFLM

Bit 3: RFLM.

NART

Bit 4: NART.

AWUM

Bit 5: AWUM.

ABOM

Bit 6: ABOM.

TTCM

Bit 7: TTCM.

RESET

Bit 15: RESET.

DBF

Bit 16: DBF.

MSR

master status register

Offset: 0x4, reset: 0x00000000, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX
r
SAMP
r
RXM
r
TXM
r
SLAKI
rw
WKUI
rw
ERRI
rw
SLAK
r
INAK
r
Toggle Fields.

INAK

Bit 0: INAK.

SLAK

Bit 1: SLAK.

ERRI

Bit 2: ERRI.

WKUI

Bit 3: WKUI.

SLAKI

Bit 4: SLAKI.

TXM

Bit 8: TXM.

RXM

Bit 9: RXM.

SAMP

Bit 10: SAMP.

RX

Bit 11: RX.

TSR

transmit status register

Offset: 0x8, reset: 0x00000000, access: Unspecified

7/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOW2
r
LOW1
r
LOW0
r
TME2
r
TME1
r
TME0
r
CODE
r
ABRQ2
rw
TERR2
rw
ALST2
rw
TXOK2
rw
RQCP2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRQ1
rw
TERR1
rw
ALST1
rw
TXOK1
rw
RQCP1
rw
ABRQ0
rw
TERR0
rw
ALST0
rw
TXOK0
rw
RQCP0
rw
Toggle Fields.

RQCP0

Bit 0: RQCP0.

TXOK0

Bit 1: TXOK0.

ALST0

Bit 2: ALST0.

TERR0

Bit 3: TERR0.

ABRQ0

Bit 7: ABRQ0.

RQCP1

Bit 8: RQCP1.

TXOK1

Bit 9: TXOK1.

ALST1

Bit 10: ALST1.

TERR1

Bit 11: TERR1.

ABRQ1

Bit 15: ABRQ1.

RQCP2

Bit 16: RQCP2.

TXOK2

Bit 17: TXOK2.

ALST2

Bit 18: ALST2.

TERR2

Bit 19: TERR2.

ABRQ2

Bit 23: ABRQ2.

CODE

Bits 24-25: CODE.

TME0

Bit 26: Lowest priority flag for mailbox 0.

TME1

Bit 27: Lowest priority flag for mailbox 1.

TME2

Bit 28: Lowest priority flag for mailbox 2.

LOW0

Bit 29: Lowest priority flag for mailbox 0.

LOW1

Bit 30: Lowest priority flag for mailbox 1.

LOW2

Bit 31: Lowest priority flag for mailbox 2.

RF%sR

receive FIFO 0 register

Offset: 0xC, reset: 0x00000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFOM
rw
FOVR
rw
FULL
rw
FMP
r
Toggle Fields.

FMP

Bits 0-1: FMP0.

FULL

Bit 3: FULL0.

Allowed values:
0: NotFull: FIFO x is not full
1: Full: FIFO x is full

FOVR

Bit 4: FOVR0.

Allowed values:
0: NoOverrun: No FIFO x overrun
1: Overrun: FIFO x overrun

RFOM

Bit 5: RFOM0.

Allowed values:
1: Release: Set by software to release the output mailbox of the FIFO

IER

interrupt enable register

Offset: 0x14, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLKIE
rw
WKUIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw
LECIE
rw
BOFIE
rw
EPVIE
rw
EWGIE
rw
FOVIE1
rw
FFIE1
rw
FMPIE1
rw
FOVIE0
rw
FFIE0
rw
FMPIE0
rw
TMEIE
rw
Toggle Fields.

TMEIE

Bit 0: TMEIE.

Allowed values:
0: Disabled: No interrupt when RQCPx bit is set
1: Enabled: Interrupt generated when RQCPx bit is set

FMPIE0

Bit 1: FMPIE0.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

FFIE0

Bit 2: FFIE0.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

FOVIE0

Bit 3: FOVIE0.

Allowed values:
0: Disabled: No interrupt when FOVR bit is set
1: Enabled: Interrupt generated when FOVR bit is set

FMPIE1

Bit 4: FMPIE1.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00b
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

FFIE1

Bit 5: FFIE1.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

FOVIE1

Bit 6: FOVIE1.

Allowed values:
0: Disabled: No interrupt when FOVR is set
1: Enabled: Interrupt generation when FOVR is set

EWGIE

Bit 8: EWGIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EWGF is set
1: Enabled: ERRI bit will be set when EWGF is set

EPVIE

Bit 9: EPVIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EPVF is set
1: Enabled: ERRI bit will be set when EPVF is set

BOFIE

Bit 10: BOFIE.

Allowed values:
0: Disabled: ERRI bit will not be set when BOFF is set
1: Enabled: ERRI bit will be set when BOFF is set

LECIE

Bit 11: LECIE.

Allowed values:
0: Disabled: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection
1: Enabled: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection

ERRIE

Bit 15: ERRIE.

Allowed values:
0: Disabled: No interrupt will be generated when an error condition is pending in the CAN_ESR
1: Enabled: An interrupt will be generation when an error condition is pending in the CAN_ESR

WKUIE

Bit 16: WKUIE.

Allowed values:
0: Disabled: No interrupt when WKUI is set
1: Enabled: Interrupt generated when WKUI bit is set

SLKIE

Bit 17: SLKIE.

Allowed values:
0: Disabled: No interrupt when SLAKI bit is set
1: Enabled: Interrupt generated when SLAKI bit is set

ESR

interrupt enable register

Offset: 0x18, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REC
r
TEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEC
rw
BOFF
r
EPVF
r
EWGF
r
Toggle Fields.

EWGF

Bit 0: EWGF.

EPVF

Bit 1: EPVF.

BOFF

Bit 2: BOFF.

LEC

Bits 4-6: LEC.

Allowed values:
0: NoError: No Error
1: Stuff: Stuff Error
2: Form: Form Error
3: Ack: Acknowledgment Error
4: BitRecessive: Bit recessive Error
5: BitDominant: Bit dominant Error
6: Crc: CRC Error
7: Custom: Set by software

TEC

Bits 16-23: TEC.

REC

Bits 24-31: REC.

BTR

bit timing register

Offset: 0x1C, reset: 0x00000000, access: read-write

2/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SILM
rw
LBKM
rw
SJW
rw
TS2
rw
TS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRP
rw
Toggle Fields.

BRP

Bits 0-9: BRP.

TS1

Bits 16-19: TS1.

TS2

Bits 20-22: TS2.

SJW

Bits 24-25: SJW.

LBKM

Bit 30: LBKM.

Allowed values:
0: Disabled: Loop Back Mode disabled
1: Enabled: Loop Back Mode enabled

SILM

Bit 31: SILM.

Allowed values:
0: Normal: Normal operation
1: Silent: Silent Mode

FMR

filter master register

Offset: 0x200, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAN2SB
rw
FINIT
rw
Toggle Fields.

FINIT

Bit 0: FINIT.

CAN2SB

Bits 8-13: CAN2SB.

FM1R

filter mode register

Offset: 0x204, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FBM27
rw
FBM26
rw
FBM25
rw
FBM24
rw
FBM23
rw
FBM22
rw
FBM21
rw
FBM20
rw
FBM19
rw
FBM18
rw
FBM17
rw
FBM16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FBM15
rw
FBM14
rw
FBM13
rw
FBM12
rw
FBM11
rw
FBM10
rw
FBM9
rw
FBM8
rw
FBM7
rw
FBM6
rw
FBM5
rw
FBM4
rw
FBM3
rw
FBM2
rw
FBM1
rw
FBM0
rw
Toggle Fields.

FBM0

Bit 0: Filter mode.

FBM1

Bit 1: Filter mode.

FBM2

Bit 2: Filter mode.

FBM3

Bit 3: Filter mode.

FBM4

Bit 4: Filter mode.

FBM5

Bit 5: Filter mode.

FBM6

Bit 6: Filter mode.

FBM7

Bit 7: Filter mode.

FBM8

Bit 8: Filter mode.

FBM9

Bit 9: Filter mode.

FBM10

Bit 10: Filter mode.

FBM11

Bit 11: Filter mode.

FBM12

Bit 12: Filter mode.

FBM13

Bit 13: Filter mode.

FBM14

Bit 14: Filter mode.

FBM15

Bit 15: Filter mode.

FBM16

Bit 16: Filter mode.

FBM17

Bit 17: Filter mode.

FBM18

Bit 18: Filter mode.

FBM19

Bit 19: Filter mode.

FBM20

Bit 20: Filter mode.

FBM21

Bit 21: Filter mode.

FBM22

Bit 22: Filter mode.

FBM23

Bit 23: Filter mode.

FBM24

Bit 24: Filter mode.

FBM25

Bit 25: Filter mode.

FBM26

Bit 26: Filter mode.

FBM27

Bit 27: Filter mode.

FS1R

filter scale register

Offset: 0x20C, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSC27
rw
FSC26
rw
FSC25
rw
FSC24
rw
FSC23
rw
FSC22
rw
FSC21
rw
FSC20
rw
FSC19
rw
FSC18
rw
FSC17
rw
FSC16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSC15
rw
FSC14
rw
FSC13
rw
FSC12
rw
FSC11
rw
FSC10
rw
FSC9
rw
FSC8
rw
FSC7
rw
FSC6
rw
FSC5
rw
FSC4
rw
FSC3
rw
FSC2
rw
FSC1
rw
FSC0
rw
Toggle Fields.

FSC0

Bit 0: Filter scale configuration.

FSC1

Bit 1: Filter scale configuration.

FSC2

Bit 2: Filter scale configuration.

FSC3

Bit 3: Filter scale configuration.

FSC4

Bit 4: Filter scale configuration.

FSC5

Bit 5: Filter scale configuration.

FSC6

Bit 6: Filter scale configuration.

FSC7

Bit 7: Filter scale configuration.

FSC8

Bit 8: Filter scale configuration.

FSC9

Bit 9: Filter scale configuration.

FSC10

Bit 10: Filter scale configuration.

FSC11

Bit 11: Filter scale configuration.

FSC12

Bit 12: Filter scale configuration.

FSC13

Bit 13: Filter scale configuration.

FSC14

Bit 14: Filter scale configuration.

FSC15

Bit 15: Filter scale configuration.

FSC16

Bit 16: Filter scale configuration.

FSC17

Bit 17: Filter scale configuration.

FSC18

Bit 18: Filter scale configuration.

FSC19

Bit 19: Filter scale configuration.

FSC20

Bit 20: Filter scale configuration.

FSC21

Bit 21: Filter scale configuration.

FSC22

Bit 22: Filter scale configuration.

FSC23

Bit 23: Filter scale configuration.

FSC24

Bit 24: Filter scale configuration.

FSC25

Bit 25: Filter scale configuration.

FSC26

Bit 26: Filter scale configuration.

FSC27

Bit 27: Filter scale configuration.

FFA1R

filter FIFO assignment register

Offset: 0x214, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FFA27
rw
FFA26
rw
FFA25
rw
FFA24
rw
FFA23
rw
FFA22
rw
FFA21
rw
FFA20
rw
FFA19
rw
FFA18
rw
FFA17
rw
FFA16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFA15
rw
FFA14
rw
FFA13
rw
FFA12
rw
FFA11
rw
FFA10
rw
FFA9
rw
FFA8
rw
FFA7
rw
FFA6
rw
FFA5
rw
FFA4
rw
FFA3
rw
FFA2
rw
FFA1
rw
FFA0
rw
Toggle Fields.

FFA0

Bit 0: Filter FIFO assignment for filter 0.

FFA1

Bit 1: Filter FIFO assignment for filter 1.

FFA2

Bit 2: Filter FIFO assignment for filter 2.

FFA3

Bit 3: Filter FIFO assignment for filter 3.

FFA4

Bit 4: Filter FIFO assignment for filter 4.

FFA5

Bit 5: Filter FIFO assignment for filter 5.

FFA6

Bit 6: Filter FIFO assignment for filter 6.

FFA7

Bit 7: Filter FIFO assignment for filter 7.

FFA8

Bit 8: Filter FIFO assignment for filter 8.

FFA9

Bit 9: Filter FIFO assignment for filter 9.

FFA10

Bit 10: Filter FIFO assignment for filter 10.

FFA11

Bit 11: Filter FIFO assignment for filter 11.

FFA12

Bit 12: Filter FIFO assignment for filter 12.

FFA13

Bit 13: Filter FIFO assignment for filter 13.

FFA14

Bit 14: Filter FIFO assignment for filter 14.

FFA15

Bit 15: Filter FIFO assignment for filter 15.

FFA16

Bit 16: Filter FIFO assignment for filter 16.

FFA17

Bit 17: Filter FIFO assignment for filter 17.

FFA18

Bit 18: Filter FIFO assignment for filter 18.

FFA19

Bit 19: Filter FIFO assignment for filter 19.

FFA20

Bit 20: Filter FIFO assignment for filter 20.

FFA21

Bit 21: Filter FIFO assignment for filter 21.

FFA22

Bit 22: Filter FIFO assignment for filter 22.

FFA23

Bit 23: Filter FIFO assignment for filter 23.

FFA24

Bit 24: Filter FIFO assignment for filter 24.

FFA25

Bit 25: Filter FIFO assignment for filter 25.

FFA26

Bit 26: Filter FIFO assignment for filter 26.

FFA27

Bit 27: Filter FIFO assignment for filter 27.

FA1R

filter activation register

Offset: 0x21C, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FACT27
rw
FACT26
rw
FACT25
rw
FACT24
rw
FACT23
rw
FACT22
rw
FACT21
rw
FACT20
rw
FACT19
rw
FACT18
rw
FACT17
rw
FACT16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FACT15
rw
FACT14
rw
FACT13
rw
FACT12
rw
FACT11
rw
FACT10
rw
FACT9
rw
FACT8
rw
FACT7
rw
FACT6
rw
FACT5
rw
FACT4
rw
FACT3
rw
FACT2
rw
FACT1
rw
FACT0
rw
Toggle Fields.

FACT0

Bit 0: Filter active.

FACT1

Bit 1: Filter active.

FACT2

Bit 2: Filter active.

FACT3

Bit 3: Filter active.

FACT4

Bit 4: Filter active.

FACT5

Bit 5: Filter active.

FACT6

Bit 6: Filter active.

FACT7

Bit 7: Filter active.

FACT8

Bit 8: Filter active.

FACT9

Bit 9: Filter active.

FACT10

Bit 10: Filter active.

FACT11

Bit 11: Filter active.

FACT12

Bit 12: Filter active.

FACT13

Bit 13: Filter active.

FACT14

Bit 14: Filter active.

FACT15

Bit 15: Filter active.

FACT16

Bit 16: Filter active.

FACT17

Bit 17: Filter active.

FACT18

Bit 18: Filter active.

FACT19

Bit 19: Filter active.

FACT20

Bit 20: Filter active.

FACT21

Bit 21: Filter active.

FACT22

Bit 22: Filter active.

FACT23

Bit 23: Filter active.

FACT24

Bit 24: Filter active.

FACT25

Bit 25: Filter active.

FACT26

Bit 26: Filter active.

FACT27

Bit 27: Filter active.

CRC

0x40023000: cyclic redundancy check calculation unit

3/3 fields covered. Toggle Registers.

DR

Data register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-31: Data register bits.

Allowed values: 0-4294967295

IDR

Independent data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle Fields.

IDR

Bits 0-7: General-purpose 8-bit data register bits.

Allowed values: 0-255

CR

Control register

Offset: 0x8, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET
w
Toggle Fields.

RESET

Bit 0: reset bit.

Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF

CRYP

0x50060000: Cryptographic processor

10/25 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: Unspecified

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRYPEN
rw
FFLUSH
w
KEYSIZE
rw
DATATYPE
rw
ALGOMODE
rw
ALGODIR
rw
Toggle Fields.

ALGODIR

Bit 2: Algorithm direction.

ALGOMODE

Bits 3-5: Algorithm mode.

DATATYPE

Bits 6-7: Data type selection.

KEYSIZE

Bits 8-9: Key size selection (AES mode only).

FFLUSH

Bit 14: FIFO flush.

CRYPEN

Bit 15: Cryptographic processor enable.

SR

status register

Offset: 0x4, reset: 0x00000003, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
OFFU
r
OFNE
r
IFNF
r
IFEM
r
Toggle Fields.

IFEM

Bit 0: Input FIFO empty.

IFNF

Bit 1: Input FIFO not full.

OFNE

Bit 2: Output FIFO not empty.

OFFU

Bit 3: Output FIFO full.

BUSY

Bit 4: Busy bit.

DIN

data input register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN
rw
Toggle Fields.

DATAIN

Bits 0-31: Data input.

DOUT

data output register

Offset: 0xC, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAOUT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAOUT
r
Toggle Fields.

DATAOUT

Bits 0-31: Data output.

DMACR

DMA control register

Offset: 0x10, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOEN
rw
DIEN
rw
Toggle Fields.

DIEN

Bit 0: DMA input enable.

DOEN

Bit 1: DMA output enable.

IMSCR

interrupt mask set/clear register

Offset: 0x14, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTIM
rw
INIM
rw
Toggle Fields.

INIM

Bit 0: Input FIFO service interrupt mask.

OUTIM

Bit 1: Output FIFO service interrupt mask.

RISR

raw interrupt status register

Offset: 0x18, reset: 0x00000001, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTRIS
r
INRIS
r
Toggle Fields.

INRIS

Bit 0: Input FIFO service raw interrupt status.

OUTRIS

Bit 1: Output FIFO service raw interrupt status.

MISR

masked interrupt status register

Offset: 0x1C, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTMIS
r
INMIS
r
Toggle Fields.

INMIS

Bit 0: Input FIFO service masked interrupt status.

OUTMIS

Bit 1: Output FIFO service masked interrupt status.

DAC

0x40007400: Digital-to-analog converter

34/34 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAUDRIE2
rw
DMAEN2
rw
MAMP2
rw
WAVE2
rw
TSEL2
rw
TEN2
rw
BOFF2
rw
EN2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAUDRIE1
rw
DMAEN1
rw
MAMP1
rw
WAVE1
rw
TSEL1
rw
TEN1
rw
BOFF1
rw
EN1
rw
Toggle Fields.

EN1

Bit 0: DAC channel1 enable.

Allowed values:
0: Disabled: DAC channel X disabled
1: Enabled: DAC channel X enabled

BOFF1

Bit 1: DAC channel1 output buffer disable.

Allowed values:
0: Enabled: DAC channel X output buffer enabled
1: Disabled: DAC channel X output buffer disabled

TEN1

Bit 2: DAC channel1 trigger enable.

Allowed values:
0: Disabled: DAC channel X trigger disabled
1: Enabled: DAC channel X trigger enabled

TSEL1

Bits 3-5: DAC channel1 trigger selection.

Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM3_TRGO: Timer 3 TRGO event
2: TIM7_TRGO: Timer 7 TRGO event
3: TIM15_TRGO: Timer 15 TRGO event
4: TIM2_TRGO: Timer 2 TRGO event
6: EXTI9: EXTI line9
7: SOFTWARE: Software trigger

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2: Triangle: Triangle wave generation enabled

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector.

Allowed values: 0-15

DMAEN1

Bit 12: DAC channel1 DMA enable.

Allowed values:
0: Disabled: DAC channel X DMA mode disabled
1: Enabled: DAC channel X DMA mode enabled

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

EN2

Bit 16: DAC channel2 enable.

Allowed values:
0: Disabled: DAC channel X disabled
1: Enabled: DAC channel X enabled

BOFF2

Bit 17: DAC channel2 output buffer disable.

Allowed values:
0: Enabled: DAC channel X output buffer enabled
1: Disabled: DAC channel X output buffer disabled

TEN2

Bit 18: DAC channel2 trigger enable.

Allowed values:
0: Disabled: DAC channel X trigger disabled
1: Enabled: DAC channel X trigger enabled

TSEL2

Bits 19-21: DAC channel2 trigger selection.

Allowed values:
0: TIM6_TRGO: Timer 6 TRGO event
1: TIM8_TRGO: Timer 8 TRGO event
2: TIM7_TRGO: Timer 7 TRGO event
3: TIM5_TRGO: Timer 5 TRGO event
4: TIM2_TRGO: Timer 2 TRGO event
5: TIM4_TRGO: Timer 4 TRGO event
6: EXTI9: EXTI line9
7: SOFTWARE: Software trigger

WAVE2

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2: Triangle: Triangle wave generation enabled

MAMP2

Bits 24-27: DAC channel2 mask/amplitude selector.

Allowed values: 0-15

DMAEN2

Bit 28: DAC channel2 DMA enable.

Allowed values:
0: Disabled: DAC channel X DMA mode disabled
1: Enabled: DAC channel X DMA mode enabled

DMAUDRIE2

Bit 29: DAC channel2 DMA underrun interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

SWTRIGR

software trigger register

Offset: 0x4, reset: 0x00000000, access: write-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG2
w
SWTRIG1
w
Toggle Fields.

SWTRIG1

Bit 0: DAC channel1 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

SWTRIG2

Bit 1: DAC channel2 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

DHR12R1

channel1 12-bit right-aligned data holding register

Offset: 0x8, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0-4095

DHR12L1

channel1 12-bit left aligned data holding register

Offset: 0xC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0-4095

DHR8R1

channel1 8-bit right aligned data holding register

Offset: 0x10, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0-255

DHR12R2

channel2 12-bit right aligned data holding register

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle Fields.

DACC2DHR

Bits 0-11: DAC channel2 12-bit right-aligned data.

Allowed values: 0-4095

DHR12L2

channel2 12-bit left aligned data holding register

Offset: 0x18, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle Fields.

DACC2DHR

Bits 4-15: DAC channel2 12-bit left-aligned data.

Allowed values: 0-4095

DHR8R2

channel2 8-bit right-aligned data holding register

Offset: 0x1C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle Fields.

DACC2DHR

Bits 0-7: DAC channel2 8-bit right-aligned data.

Allowed values: 0-255

DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0-4095

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data.

Allowed values: 0-4095

DHR12LD

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0-4095

DACC2DHR

Bits 20-31: DAC channel2 12-bit left-aligned data.

Allowed values: 0-4095

DHR8RD

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0-255

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data.

Allowed values: 0-255

DOR1

channel1 data output register

Offset: 0x2C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DOR
r
Toggle Fields.

DACC1DOR

Bits 0-11: DAC channel1 data output.

DOR2

channel2 data output register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DOR
r
Toggle Fields.

DACC2DOR

Bits 0-11: DAC channel2 data output.

SR

status register

Offset: 0x34, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAUDR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAUDR1
rw
Toggle Fields.

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel X
1: Underrun: DMA underrun error condition occurred for DAC channel X

DMAUDR2

Bit 29: DAC channel2 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel X
1: Underrun: DMA underrun error condition occurred for DAC channel X

DBGMCU

0xE0042000: Debug support

2/28 fields covered. Toggle Registers.

IDCODE

IDCODE

Offset: 0x0, reset: 0x10006411, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEV_ID
r
Toggle Fields.

DEV_ID

Bits 0-11: DEV_ID.

REV_ID

Bits 16-31: REV_ID.

CR

Control Register

Offset: 0x4, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRACE_MODE
rw
TRACE_IOEN
rw
DBG_STANDBY
rw
DBG_STOP
rw
DBG_SLEEP
rw
Toggle Fields.

DBG_SLEEP

Bit 0: DBG_SLEEP.

DBG_STOP

Bit 1: DBG_STOP.

DBG_STANDBY

Bit 2: DBG_STANDBY.

TRACE_IOEN

Bit 5: TRACE_IOEN.

TRACE_MODE

Bits 6-7: TRACE_MODE.

APB1_FZ

Debug MCU APB1 Freeze registe

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

DBG_TIM2_STOP

Bit 0: DBG_TIM2_STOP.

DBG_TIM3_STOP

Bit 1: DBG_TIM3 _STOP.

DBG_TIM4_STOP

Bit 2: DBG_TIM4_STOP.

DBG_TIM5_STOP

Bit 3: DBG_TIM5_STOP.

DBG_TIM6_STOP

Bit 4: DBG_TIM6_STOP.

DBG_TIM7_STOP

Bit 5: DBG_TIM7_STOP.

DBG_TIM12_STOP

Bit 6: DBG_TIM12_STOP.

DBG_TIM13_STOP

Bit 7: DBG_TIM13_STOP.

DBG_TIM14_STOP

Bit 8: DBG_TIM14_STOP.

DBG_WWDG_STOP

Bit 11: DBG_WWDG_STOP.

DBG_IWDG_STOP

Bit 12: DBG_IWDEG_STOP.

DBG_J2C1_SMBUS_TIMEOUT

Bit 21: DBG_J2C1_SMBUS_TIMEOUT.

DBG_J2C2_SMBUS_TIMEOUT

Bit 22: DBG_J2C2_SMBUS_TIMEOUT.

DBG_J2C3SMBUS_TIMEOUT

Bit 23: DBG_J2C3SMBUS_TIMEOUT.

DBG_CAN1_STOP

Bit 25: DBG_CAN1_STOP.

DBG_CAN2_STOP

Bit 26: DBG_CAN2_STOP.

APB2_FZ

Debug MCU APB2 Freeze registe

Offset: 0xC, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_TIM11_STOP
rw
DBG_TIM10_STOP
rw
DBG_TIM9_STOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_TIM8_STOP
rw
DBG_TIM1_STOP
rw
Toggle Fields.

DBG_TIM1_STOP

Bit 0: TIM1 counter stopped when core is halted.

DBG_TIM8_STOP

Bit 1: TIM8 counter stopped when core is halted.

DBG_TIM9_STOP

Bit 16: TIM9 counter stopped when core is halted.

DBG_TIM10_STOP

Bit 17: TIM10 counter stopped when core is halted.

DBG_TIM11_STOP

Bit 18: TIM11 counter stopped when core is halted.

DCMI

0x50050000: Digital camera interface

17/50 fields covered. Toggle Registers.

CR

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABLE
rw
EDM
rw
FCRC
rw
VSPOL
rw
HSPOL
rw
PCKPOL
rw
ESS
rw
JPEG
rw
CROP
rw
CM
rw
CAPTURE
rw
Toggle Fields.

CAPTURE

Bit 0: Capture enable.

CM

Bit 1: Capture mode.

CROP

Bit 2: Crop feature.

JPEG

Bit 3: JPEG format.

ESS

Bit 4: Embedded synchronization select.

PCKPOL

Bit 5: Pixel clock polarity.

HSPOL

Bit 6: Horizontal synchronization polarity.

VSPOL

Bit 7: Vertical synchronization polarity.

FCRC

Bits 8-9: Frame capture rate control.

EDM

Bits 10-11: Extended data mode.

ENABLE

Bit 14: DCMI enable.

SR

status register

Offset: 0x4, reset: 0x0000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNE
r
VSYNC
r
HSYNC
r
Toggle Fields.

HSYNC

Bit 0: HSYNC.

VSYNC

Bit 1: VSYNC.

FNE

Bit 2: FIFO not empty.

RIS

raw interrupt status register

Offset: 0x8, reset: 0x0000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_RIS
r
VSYNC_RIS
r
ERR_RIS
r
OVR_RIS
r
FRAME_RIS
r
Toggle Fields.

FRAME_RIS

Bit 0: Capture complete raw interrupt status.

OVR_RIS

Bit 1: Overrun raw interrupt status.

ERR_RIS

Bit 2: Synchronization error raw interrupt status.

VSYNC_RIS

Bit 3: VSYNC raw interrupt status.

LINE_RIS

Bit 4: Line raw interrupt status.

IER

interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_IE
rw
VSYNC_IE
rw
ERR_IE
rw
OVR_IE
rw
FRAME_IE
rw
Toggle Fields.

FRAME_IE

Bit 0: Capture complete interrupt enable.

OVR_IE

Bit 1: Overrun interrupt enable.

ERR_IE

Bit 2: Synchronization error interrupt enable.

VSYNC_IE

Bit 3: VSYNC interrupt enable.

LINE_IE

Bit 4: Line interrupt enable.

MIS

masked interrupt status register

Offset: 0x10, reset: 0x0000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_MIS
r
VSYNC_MIS
r
ERR_MIS
r
OVR_MIS
r
FRAME_MIS
r
Toggle Fields.

FRAME_MIS

Bit 0: Capture complete masked interrupt status.

OVR_MIS

Bit 1: Overrun masked interrupt status.

ERR_MIS

Bit 2: Synchronization error masked interrupt status.

VSYNC_MIS

Bit 3: VSYNC masked interrupt status.

LINE_MIS

Bit 4: Line masked interrupt status.

ICR

interrupt clear register

Offset: 0x14, reset: 0x0000, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_ISC
w
VSYNC_ISC
w
ERR_ISC
w
OVR_ISC
w
FRAME_ISC
w
Toggle Fields.

FRAME_ISC

Bit 0: Capture complete interrupt status clear.

OVR_ISC

Bit 1: Overrun interrupt status clear.

ERR_ISC

Bit 2: Synchronization error interrupt status clear.

VSYNC_ISC

Bit 3: Vertical synch interrupt status clear.

LINE_ISC

Bit 4: line interrupt status clear.

ESCR

embedded synchronization code register

Offset: 0x18, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEC
rw
LEC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSC
rw
FSC
rw
Toggle Fields.

FSC

Bits 0-7: Frame start delimiter code.

LSC

Bits 8-15: Line start delimiter code.

LEC

Bits 16-23: Line end delimiter code.

FEC

Bits 24-31: Frame end delimiter code.

ESUR

embedded synchronization unmask register

Offset: 0x1C, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEU
rw
LEU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSU
rw
FSU
rw
Toggle Fields.

FSU

Bits 0-7: Frame start delimiter unmask.

LSU

Bits 8-15: Line start delimiter unmask.

LEU

Bits 16-23: Line end delimiter unmask.

FEU

Bits 24-31: Frame end delimiter unmask.

CWSTRT

crop window start

Offset: 0x20, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HOFFCNT
rw
Toggle Fields.

HOFFCNT

Bits 0-13: Horizontal offset count.

VST

Bits 16-28: Vertical start line count.

CWSIZE

crop window size

Offset: 0x24, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VLINE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPCNT
rw
Toggle Fields.

CAPCNT

Bits 0-13: Capture count.

VLINE

Bits 16-29: Vertical line count.

DR

data register

Offset: 0x28, reset: 0x0000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Byte3
r
Byte2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Byte1
r
Byte0
r
Toggle Fields.

Byte0

Bits 0-7: Data byte 0.

Byte1

Bits 8-15: Data byte 1.

Byte2

Bits 16-23: Data byte 2.

Byte3

Bits 24-31: Data byte 3.

DMA1

0x40026000: DMA controller

104/107 fields covered. Toggle Registers.

LISR

low interrupt status register

Offset: 0x0, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCIF3
r
HTIF3
r
TEIF3
r
DMEIF3
r
FEIF3
r
TCIF2
r
HTIF2
r
TEIF2
r
DMEIF2
r
FEIF2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF1
r
HTIF1
r
TEIF1
r
DMEIF1
r
FEIF1
r
TCIF0
r
HTIF0
r
TEIF0
r
DMEIF0
r
FEIF0
r
Toggle Fields.

FEIF0

Bit 0: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF0

Bit 2: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF0

Bit 3: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF0

Bit 4: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF0

Bit 5: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF1

Bit 6: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF1

Bit 8: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF1

Bit 9: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF1

Bit 10: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF1

Bit 11: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF2

Bit 16: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF2

Bit 18: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF2

Bit 19: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF2

Bit 20: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF2

Bit 21: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF3

Bit 22: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF3

Bit 24: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF3

Bit 25: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF3

Bit 26: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF3

Bit 27: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

HISR

high interrupt status register

Offset: 0x4, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCIF7
r
HTIF7
r
TEIF7
r
DMEIF7
r
FEIF7
r
TCIF6
r
HTIF6
r
TEIF6
r
DMEIF6
r
FEIF6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF5
r
HTIF5
r
TEIF5
r
DMEIF5
r
FEIF5
r
TCIF4
r
HTIF4
r
TEIF4
r
DMEIF4
r
FEIF4
r
Toggle Fields.

FEIF4

Bit 0: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF4

Bit 2: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF4

Bit 3: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF4

Bit 4: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF4

Bit 5: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF5

Bit 6: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF5

Bit 8: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF5

Bit 9: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF5

Bit 10: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF5

Bit 11: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF6

Bit 16: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF6

Bit 18: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF6

Bit 19: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF6

Bit 20: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF6

Bit 21: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF7

Bit 22: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF7

Bit 24: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF7

Bit 25: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF7

Bit 26: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF7

Bit 27: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

LIFCR

low interrupt flag clear register

Offset: 0x8, reset: 0x00000000, access: write-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTCIF3
w
CHTIF3
w
CTEIF3
w
CDMEIF3
w
CFEIF3
w
CTCIF2
w
CHTIF2
w
CTEIF2
w
CDMEIF2
w
CFEIF2
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTCIF1
w
CHTIF1
w
CTEIF1
w
CDMEIF1
w
CFEIF1
w
CTCIF0
w
CHTIF0
w
CTEIF0
w
CDMEIF0
w
CFEIF0
w
Toggle Fields.

CFEIF0

Bit 0: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF0

Bit 2: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF0

Bit 3: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF0

Bit 4: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF0

Bit 5: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF1

Bit 6: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF1

Bit 8: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF1

Bit 9: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF1

Bit 10: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF1

Bit 11: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF2

Bit 16: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF2

Bit 18: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF2

Bit 19: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF2

Bit 20: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF2

Bit 21: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF3

Bit 22: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF3

Bit 24: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF3

Bit 25: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF3

Bit 26: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF3

Bit 27: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

HIFCR

high interrupt flag clear register

Offset: 0xC, reset: 0x00000000, access: write-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTCIF7
w
CHTIF7
w
CTEIF7
w
CDMEIF7
w
CFEIF7
w
CTCIF6
w
CHTIF6
w
CTEIF6
w
CDMEIF6
w
CFEIF6
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTCIF5
w
CHTIF5
w
CTEIF5
w
CDMEIF5
w
CFEIF5
w
CTCIF4
w
CHTIF4
w
CTEIF4
w
CDMEIF4
w
CFEIF4
w
Toggle Fields.

CFEIF4

Bit 0: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF4

Bit 2: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF4

Bit 3: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF4

Bit 4: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF4

Bit 5: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF5

Bit 6: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF5

Bit 8: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF5

Bit 9: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF5

Bit 10: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF5

Bit 11: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF6

Bit 16: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF6

Bit 18: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF6

Bit 19: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF6

Bit 20: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF6

Bit 21: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF7

Bit 22: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF7

Bit 24: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF7

Bit 25: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF7

Bit 26: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF7

Bit 27: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

M1AR

stream x memory 1 address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle Fields.

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR

stream x FIFO control register

Offset: 0x14, reset: 0x00000021, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle Fields.

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

DMA2

0x40026400: DMA controller

104/107 fields covered. Toggle Registers.

LISR

low interrupt status register

Offset: 0x0, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCIF3
r
HTIF3
r
TEIF3
r
DMEIF3
r
FEIF3
r
TCIF2
r
HTIF2
r
TEIF2
r
DMEIF2
r
FEIF2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF1
r
HTIF1
r
TEIF1
r
DMEIF1
r
FEIF1
r
TCIF0
r
HTIF0
r
TEIF0
r
DMEIF0
r
FEIF0
r
Toggle Fields.

FEIF0

Bit 0: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF0

Bit 2: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF0

Bit 3: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF0

Bit 4: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF0

Bit 5: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF1

Bit 6: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF1

Bit 8: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF1

Bit 9: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF1

Bit 10: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF1

Bit 11: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF2

Bit 16: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF2

Bit 18: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF2

Bit 19: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF2

Bit 20: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF2

Bit 21: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF3

Bit 22: Stream x FIFO error interrupt flag (x=3..0).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF3

Bit 24: Stream x direct mode error interrupt flag (x=3..0).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF3

Bit 25: Stream x transfer error interrupt flag (x=3..0).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF3

Bit 26: Stream x half transfer interrupt flag (x=3..0).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF3

Bit 27: Stream x transfer complete interrupt flag (x = 3..0).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

HISR

high interrupt status register

Offset: 0x4, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCIF7
r
HTIF7
r
TEIF7
r
DMEIF7
r
FEIF7
r
TCIF6
r
HTIF6
r
TEIF6
r
DMEIF6
r
FEIF6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF5
r
HTIF5
r
TEIF5
r
DMEIF5
r
FEIF5
r
TCIF4
r
HTIF4
r
TEIF4
r
DMEIF4
r
FEIF4
r
Toggle Fields.

FEIF4

Bit 0: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF4

Bit 2: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF4

Bit 3: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF4

Bit 4: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF4

Bit 5: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF5

Bit 6: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF5

Bit 8: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF5

Bit 9: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF5

Bit 10: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF5

Bit 11: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF6

Bit 16: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF6

Bit 18: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF6

Bit 19: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF6

Bit 20: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF6

Bit 21: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

FEIF7

Bit 22: Stream x FIFO error interrupt flag (x=7..4).

Allowed values:
0: NoError: No FIFO error event on stream x
1: Error: A FIFO error event occurred on stream x

DMEIF7

Bit 24: Stream x direct mode error interrupt flag (x=7..4).

Allowed values:
0: NoError: No Direct Mode error on stream x
1: Error: A Direct Mode error occurred on stream x

TEIF7

Bit 25: Stream x transfer error interrupt flag (x=7..4).

Allowed values:
0: NoError: No transfer error on stream x
1: Error: A transfer error occurred on stream x

HTIF7

Bit 26: Stream x half transfer interrupt flag (x=7..4).

Allowed values:
0: NotHalf: No half transfer event on stream x
1: Half: A half transfer event occurred on stream x

TCIF7

Bit 27: Stream x transfer complete interrupt flag (x=7..4).

Allowed values:
0: NotComplete: No transfer complete event on stream x
1: Complete: A transfer complete event occurred on stream x

LIFCR

low interrupt flag clear register

Offset: 0x8, reset: 0x00000000, access: write-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTCIF3
w
CHTIF3
w
CTEIF3
w
CDMEIF3
w
CFEIF3
w
CTCIF2
w
CHTIF2
w
CTEIF2
w
CDMEIF2
w
CFEIF2
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTCIF1
w
CHTIF1
w
CTEIF1
w
CDMEIF1
w
CFEIF1
w
CTCIF0
w
CHTIF0
w
CTEIF0
w
CDMEIF0
w
CFEIF0
w
Toggle Fields.

CFEIF0

Bit 0: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF0

Bit 2: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF0

Bit 3: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF0

Bit 4: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF0

Bit 5: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF1

Bit 6: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF1

Bit 8: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF1

Bit 9: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF1

Bit 10: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF1

Bit 11: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF2

Bit 16: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF2

Bit 18: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF2

Bit 19: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF2

Bit 20: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF2

Bit 21: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF3

Bit 22: Stream x clear FIFO error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF3

Bit 24: Stream x clear direct mode error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF3

Bit 25: Stream x clear transfer error interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF3

Bit 26: Stream x clear half transfer interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF3

Bit 27: Stream x clear transfer complete interrupt flag (x = 3..0).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

HIFCR

high interrupt flag clear register

Offset: 0xC, reset: 0x00000000, access: write-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTCIF7
w
CHTIF7
w
CTEIF7
w
CDMEIF7
w
CFEIF7
w
CTCIF6
w
CHTIF6
w
CTEIF6
w
CDMEIF6
w
CFEIF6
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTCIF5
w
CHTIF5
w
CTEIF5
w
CDMEIF5
w
CFEIF5
w
CTCIF4
w
CHTIF4
w
CTEIF4
w
CDMEIF4
w
CFEIF4
w
Toggle Fields.

CFEIF4

Bit 0: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF4

Bit 2: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF4

Bit 3: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF4

Bit 4: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF4

Bit 5: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF5

Bit 6: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF5

Bit 8: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF5

Bit 9: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF5

Bit 10: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF5

Bit 11: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF6

Bit 16: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF6

Bit 18: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF6

Bit 19: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF6

Bit 20: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF6

Bit 21: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

CFEIF7

Bit 22: Stream x clear FIFO error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding CFEIFx flag

CDMEIF7

Bit 24: Stream x clear direct mode error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding DMEIFx flag

CTEIF7

Bit 25: Stream x clear transfer error interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TEIFx flag

CHTIF7

Bit 26: Stream x clear half transfer interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding HTIFx flag

CTCIF7

Bit 27: Stream x clear transfer complete interrupt flag (x = 7..4).

Allowed values:
1: Clear: Clear the corresponding TCIFx flag

M1AR

stream x memory 1 address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle Fields.

M1A

Bits 0-31: Memory 1 address (used in case of Double buffer mode).

FCR

stream x FIFO control register

Offset: 0x14, reset: 0x00000021, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw
FS
r
DMDIS
rw
FTH
rw
Toggle Fields.

FTH

Bits 0-1: FIFO threshold selection.

Allowed values:
0: Quarter: 1/4 full FIFO
1: Half: 1/2 full FIFO
2: ThreeQuarters: 3/4 full FIFO
3: Full: Full FIFO

DMDIS

Bit 2: Direct mode disable.

Allowed values:
0: Enabled: Direct mode is enabled
1: Disabled: Direct mode is disabled

FS

Bits 3-5: FIFO status.

Allowed values:
0: Quarter1: 0 < fifo_level < 1/4
1: Quarter2: 1/4 <= fifo_level < 1/2
2: Quarter3: 1/2 <= fifo_level < 3/4
3: Quarter4: 3/4 <= fifo_level < full
4: Empty: FIFO is empty
5: Full: FIFO is full

FEIE

Bit 7: FIFO error interrupt enable.

Allowed values:
0: Disabled: FE interrupt disabled
1: Enabled: FE interrupt enabled

Ethernet_DMA

0x40029000: Ethernet: DMA controller operation

10/73 fields covered. Toggle Registers.

DMABMR

Ethernet DMA bus mode register

Offset: 0x0, reset: 0x20101, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MB
rw
AAB
rw
FPM
rw
USP
rw
RDP
rw
FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PM
rw
PBL
rw
EDFE
rw
DSL
rw
DA
rw
SR
rw
Toggle Fields.

SR

Bit 0: Software reset.

DA

Bit 1: DMA Arbitration.

DSL

Bits 2-6: Descriptor skip length.

EDFE

Bit 7: Enhanced descriptor format enable.

PBL

Bits 8-13: Programmable burst length.

PM

Bits 14-15: Rx Tx priority ratio.

FB

Bit 16: Fixed burst.

RDP

Bits 17-22: Rx DMA PBL.

USP

Bit 23: Use separate PBL.

FPM

Bit 24: 4xPBL mode.

AAB

Bit 25: Address-aligned beats.

MB

Bit 26: Mixed burst.

DMATPDR

Ethernet DMA transmit poll demand register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TPD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPD
rw
Toggle Fields.

TPD

Bits 0-31: Transmit poll demand.

DMARPDR

EHERNET DMA receive poll demand register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPD
rw
Toggle Fields.

RPD

Bits 0-31: Receive poll demand.

DMARDLAR

Ethernet DMA receive descriptor list address register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRL
rw
Toggle Fields.

SRL

Bits 0-31: Start of receive list.

DMATDLAR

Ethernet DMA transmit descriptor list address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STL
rw
Toggle Fields.

STL

Bits 0-31: Start of transmit list.

DMASR

Ethernet DMA status register

Offset: 0x14, reset: 0x00000000, access: Unspecified

6/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSTS
r
PMTS
r
MMCS
r
EBS
r
TPS
r
RPS
r
NIS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AIS
rw
ERS
rw
FBES
rw
ETS
rw
PWTS
rw
RPSS
rw
RBUS
rw
RS
rw
TUS
rw
ROS
rw
TJTS
rw
TBUS
rw
TPSS
rw
TS
rw
Toggle Fields.

TS

Bit 0: Transmit status.

TPSS

Bit 1: Transmit process stopped status.

TBUS

Bit 2: Transmit buffer unavailable status.

TJTS

Bit 3: Transmit jabber timeout status.

ROS

Bit 4: Receive overflow status.

TUS

Bit 5: Transmit underflow status.

RS

Bit 6: Receive status.

RBUS

Bit 7: Receive buffer unavailable status.

RPSS

Bit 8: Receive process stopped status.

PWTS

Bit 9: Receive watchdog timeout status.

ETS

Bit 10: Early transmit status.

FBES

Bit 13: Fatal bus error status.

ERS

Bit 14: Early receive status.

AIS

Bit 15: Abnormal interrupt summary.

NIS

Bit 16: Normal interrupt summary.

RPS

Bits 17-19: Receive process state.

TPS

Bits 20-22: Transmit process state.

EBS

Bits 23-25: Error bits status.

MMCS

Bit 27: MMC status.

PMTS

Bit 28: PMT status.

TSTS

Bit 29: Time stamp trigger status.

DMAOMR

Ethernet DMA operation mode register

Offset: 0x18, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTCEFD
rw
RSF
rw
DFRF
rw
TSF
rw
FTF
rw
TTC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTC
rw
ST
rw
FEF
rw
FUGF
rw
RTC
rw
OSF
rw
SR
rw
Toggle Fields.

SR

Bit 1: SR.

OSF

Bit 2: OSF.

RTC

Bits 3-4: RTC.

FUGF

Bit 6: FUGF.

FEF

Bit 7: FEF.

ST

Bit 13: ST.

TTC

Bits 14-16: TTC.

FTF

Bit 20: FTF.

TSF

Bit 21: TSF.

DFRF

Bit 24: DFRF.

RSF

Bit 25: RSF.

DTCEFD

Bit 26: DTCEFD.

DMAIER

Ethernet DMA interrupt enable register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NISE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AISE
rw
ERIE
rw
FBEIE
rw
ETIE
rw
RWTIE
rw
RPSIE
rw
RBUIE
rw
RIE
rw
TUIE
rw
ROIE
rw
TJTIE
rw
TBUIE
rw
TPSIE
rw
TIE
rw
Toggle Fields.

TIE

Bit 0: Transmit interrupt enable.

TPSIE

Bit 1: Transmit process stopped interrupt enable.

TBUIE

Bit 2: Transmit buffer unavailable interrupt enable.

TJTIE

Bit 3: Transmit jabber timeout interrupt enable.

ROIE

Bit 4: Overflow interrupt enable.

TUIE

Bit 5: Underflow interrupt enable.

RIE

Bit 6: Receive interrupt enable.

RBUIE

Bit 7: Receive buffer unavailable interrupt enable.

RPSIE

Bit 8: Receive process stopped interrupt enable.

RWTIE

Bit 9: receive watchdog timeout interrupt enable.

ETIE

Bit 10: Early transmit interrupt enable.

FBEIE

Bit 13: Fatal bus error interrupt enable.

ERIE

Bit 14: Early receive interrupt enable.

AISE

Bit 15: Abnormal interrupt summary enable.

NISE

Bit 16: Normal interrupt summary enable.

DMAMFBOCR

Ethernet DMA missed frame and buffer overflow counter register

Offset: 0x20, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFOC
rw
MFA
rw
OMFC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFC
rw
Toggle Fields.

MFC

Bits 0-15: Missed frames by the controller.

OMFC

Bit 16: Overflow bit for missed frame counter.

MFA

Bits 17-27: Missed frames by the application.

OFOC

Bit 28: Overflow bit for FIFO overflow counter.

DMARSWTR

Ethernet DMA receive status watchdog timer register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSWTC
rw
Toggle Fields.

RSWTC

Bits 0-7: Receive status watchdog timer count.

DMACHTDR

Ethernet DMA current host transmit descriptor register

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTDAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTDAP
r
Toggle Fields.

HTDAP

Bits 0-31: Host transmit descriptor address pointer.

DMACHRDR

Ethernet DMA current host receive descriptor register

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HRDAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HRDAP
r
Toggle Fields.

HRDAP

Bits 0-31: Host receive descriptor address pointer.

DMACHTBAR

Ethernet DMA current host transmit buffer address register

Offset: 0x50, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTBAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTBAP
r
Toggle Fields.

HTBAP

Bits 0-31: Host transmit buffer address pointer.

DMACHRBAR

Ethernet DMA current host receive buffer address register

Offset: 0x54, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HRBAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HRBAP
r
Toggle Fields.

HRBAP

Bits 0-31: Host receive buffer address pointer.

Ethernet_MAC

0x40028000: Ethernet: media access control (MAC)

17/89 fields covered. Toggle Registers.

MACCR

Ethernet MAC configuration register

Offset: 0x0, reset: 0x8000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSTF
rw
WD
rw
JD
rw
IFG
rw
CSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FES
rw
ROD
rw
LM
rw
DM
rw
IPCO
rw
RD
rw
APCS
rw
BL
rw
DC
rw
TE
rw
RE
rw
Toggle Fields.

RE

Bit 2: RE.

TE

Bit 3: TE.

DC

Bit 4: DC.

BL

Bits 5-6: BL.

APCS

Bit 7: APCS.

RD

Bit 9: RD.

IPCO

Bit 10: IPCO.

DM

Bit 11: DM.

LM

Bit 12: LM.

ROD

Bit 13: ROD.

FES

Bit 14: FES.

CSD

Bit 16: CSD.

IFG

Bits 17-19: IFG.

JD

Bit 22: JD.

WD

Bit 23: WD.

CSTF

Bit 25: CSTF.

MACFFR

Ethernet MAC frame filter register

Offset: 0x4, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HPF
rw
SAF
rw
SAIF
rw
PCF
rw
BFD
rw
PAM
rw
DAIF
rw
HM
rw
HU
rw
PM
rw
Toggle Fields.

PM

Bit 0: Promiscuous mode.

HU

Bit 1: Hash unicast.

HM

Bit 2: Hash multicast.

DAIF

Bit 3: Destination address inverse filtering.

PAM

Bit 4: Pass all multicast.

BFD

Bit 5: Broadcast frames disable.

PCF

Bits 6-7: Pass control frames.

SAIF

Bit 8: Source address inverse filtering.

SAF

Bit 9: Source address filter.

HPF

Bit 10: Hash or perfect filter.

RA

Bit 31: Receive all.

MACHTHR

Ethernet MAC hash table high register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTH
rw
Toggle Fields.

HTH

Bits 0-31: Hash table high.

MACHTLR

Ethernet MAC hash table low register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTL
rw
Toggle Fields.

HTL

Bits 0-31: Hash table low.

MACMIIAR

Ethernet MAC MII address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
MR
rw
CR
rw
MW
rw
MB
rw
Toggle Fields.

MB

Bit 0: MII busy.

MW

Bit 1: MII write.

CR

Bits 2-4: Clock range.

MR

Bits 6-10: MII register.

PA

Bits 11-15: PHY address.

MACMIIDR

Ethernet MAC MII data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MD
rw
Toggle Fields.

MD

Bits 0-15: MII data.

MACFCR

Ethernet MAC flow control register

Offset: 0x18, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ZQPD
rw
PLT
rw
UPFD
rw
RFCE
rw
TFCE
rw
FCB
rw
Toggle Fields.

FCB

Bit 0: Flow control busy/back pressure activate.

TFCE

Bit 1: Transmit flow control enable.

RFCE

Bit 2: Receive flow control enable.

UPFD

Bit 3: Unicast pause frame detect.

PLT

Bits 4-5: Pause low threshold.

ZQPD

Bit 7: Zero-quanta pause disable.

PT

Bits 16-31: Pause time.

MACVLANTR

Ethernet MAC VLAN tag register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VLANTC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLANTI
rw
Toggle Fields.

VLANTI

Bits 0-15: VLAN tag identifier.

VLANTC

Bit 16: 12-bit VLAN tag comparison.

MACRWUFFR

Ethernet MAC remote wakeup frame filter register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

MACPMTCSR

Ethernet MAC PMT control and status register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WFFRPR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GU
rw
WFR
rw
MPR
rw
WFE
rw
MPE
rw
PD
rw
Toggle Fields.

PD

Bit 0: Power down.

MPE

Bit 1: Magic Packet enable.

WFE

Bit 2: Wakeup frame enable.

MPR

Bit 5: Magic packet received.

WFR

Bit 6: Wakeup frame received.

GU

Bit 9: Global unicast.

WFFRPR

Bit 31: Wakeup frame filter register pointer reset.

MACDBGR

Ethernet MAC debug register

Offset: 0x34, reset: 0x00000000, access: read-only

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFF
r
TFNE
r
TFWA
r
TFRS
r
MTP
r
MTFCS
r
MMTEA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFFL
r
RFRCS
r
RFWRA
r
MSFRWCS
r
MMRPEA
r
Toggle Fields.

MMRPEA

Bit 0: MAC MII receive protocol engine active.

MSFRWCS

Bit 1: MAC small FIFO read / write controllers status.

RFWRA

Bit 4: Rx FIFO write controller active.

RFRCS

Bit 5: Rx FIFO read controller status.

RFFL

Bit 8: Rx FIFO fill level.

MMTEA

Bit 16: MAC MII transmit engine active.

MTFCS

Bits 17-18: MAC transmit frame controller status.

MTP

Bit 19: MAC transmitter in pause.

TFRS

Bits 20-21: Tx FIFO read status.

TFWA

Bit 22: Tx FIFO write active.

TFNE

Bit 24: Tx FIFO not empty.

TFF

Bit 25: Tx FIFO full.

MACSR

Ethernet MAC interrupt status register

Offset: 0x38, reset: 0x00000000, access: Unspecified

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSTS
rw
MMCTS
r
MMCRS
r
MMCS
r
PMTS
r
Toggle Fields.

PMTS

Bit 3: PMT status.

MMCS

Bit 4: MMC status.

MMCRS

Bit 5: MMC receive status.

MMCTS

Bit 6: MMC transmit status.

TSTS

Bit 9: Time stamp trigger status.

MACIMR

Ethernet MAC interrupt mask register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSTIM
rw
PMTIM
rw
Toggle Fields.

PMTIM

Bit 3: PMT interrupt mask.

TSTIM

Bit 9: Time stamp trigger interrupt mask.

MACA0HR

Ethernet MAC address 0 high register

Offset: 0x40, reset: 0x0010FFFF, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MO
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA0H
rw
Toggle Fields.

MACA0H

Bits 0-15: MAC address0 high.

MO

Bit 31: MO.

MACA0LR

Ethernet MAC address 0 low register

Offset: 0x44, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MACA0L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA0L
rw
Toggle Fields.

MACA0L

Bits 0-31: MAC address0 low.

MACA1HR

Ethernet MAC address 1 high register

Offset: 0x48, reset: 0xFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AE
rw
SA
rw
MBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA1H
rw
Toggle Fields.

MACA1H

Bits 0-15: MAC address1 high.

MBC

Bits 24-29: Mask byte control.

SA

Bit 30: Source address.

AE

Bit 31: Address enable.

MACA1LR

Ethernet MAC address1 low register

Offset: 0x4C, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MACA1L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA1L
rw
Toggle Fields.

MACA1L

Bits 0-31: MAC address1 low.

MACA2HR

Ethernet MAC address 2 high register

Offset: 0x50, reset: 0xFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AE
rw
SA
rw
MBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA2H
rw
Toggle Fields.

MACA2H

Bits 0-15: MAC address2 high.

MBC

Bits 24-29: Mask byte control.

SA

Bit 30: Source address.

AE

Bit 31: Address enable.

MACA2LR

Ethernet MAC address 2 low register

Offset: 0x54, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MACA2L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA2L
rw
Toggle Fields.

MACA2L

Bits 0-31: MAC address2 low.

MACA3HR

Ethernet MAC address 3 high register

Offset: 0x58, reset: 0xFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AE
rw
SA
rw
MBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA3H
rw
Toggle Fields.

MACA3H

Bits 0-15: MAC address3 high.

MBC

Bits 24-29: Mask byte control.

SA

Bit 30: Source address.

AE

Bit 31: Address enable.

MACA3LR

Ethernet MAC address 3 low register

Offset: 0x5C, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MACA3L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MACA3L
rw
Toggle Fields.

MACA3L

Bits 0-31: MAC address3 low.

Ethernet_MMC

0x40028100: Ethernet: MAC management counters

6/24 fields covered. Toggle Registers.

MMCCR

Ethernet MMC control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCFHP
rw
MCP
rw
MCF
rw
ROR
rw
CSR
rw
CR
rw
Toggle Fields.

CR

Bit 0: Counter reset.

CSR

Bit 1: Counter stop rollover.

ROR

Bit 2: Reset on read.

MCF

Bit 3: MMC counter freeze.

MCP

Bit 4: MMC counter preset.

MCFHP

Bit 5: MMC counter Full-Half preset.

MMCRIR

Ethernet MMC receive interrupt register

Offset: 0x4, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGUFS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFAES
rw
RFCES
rw
Toggle Fields.

RFCES

Bit 5: Received frames CRC error status.

RFAES

Bit 6: Received frames alignment error status.

RGUFS

Bit 17: Received Good Unicast Frames Status.

MMCTIR

Ethernet MMC transmit interrupt register

Offset: 0x8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGFS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFMSCS
rw
TGFSCS
rw
Toggle Fields.

TGFSCS

Bit 14: Transmitted good frames single collision status.

TGFMSCS

Bit 15: Transmitted good frames more single collision status.

TGFS

Bit 21: Transmitted good frames status.

MMCRIMR

Ethernet MMC receive interrupt mask register

Offset: 0xC, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGUFM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFAEM
rw
RFCEM
rw
Toggle Fields.

RFCEM

Bit 5: Received frame CRC error mask.

RFAEM

Bit 6: Received frames alignment error mask.

RGUFM

Bit 17: Received good unicast frames mask.

MMCTIMR

Ethernet MMC transmit interrupt mask register

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGFM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFMSCM
rw
TGFSCM
rw
Toggle Fields.

TGFSCM

Bit 14: Transmitted good frames single collision mask.

TGFMSCM

Bit 15: Transmitted good frames more single collision mask.

TGFM

Bit 21: Transmitted good frames mask.

MMCTGFSCCR

Ethernet MMC transmitted good frames after a single collision counter

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGFSCC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFSCC
r
Toggle Fields.

TGFSCC

Bits 0-31: Transmitted good frames single collision counter.

MMCTGFMSCCR

Ethernet MMC transmitted good frames after more than a single collision

Offset: 0x50, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGFMSCC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFMSCC
r
Toggle Fields.

TGFMSCC

Bits 0-31: Transmitted good frames more single collision counter.

MMCTGFCR

Ethernet MMC transmitted good frames counter register

Offset: 0x68, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGFC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFC
r
Toggle Fields.

TGFC

Bits 0-31: Transmitted good frames counter.

MMCRFCECR

Ethernet MMC received frames with CRC error counter register

Offset: 0x94, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RFCFC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFCFC
r
Toggle Fields.

RFCFC

Bits 0-31: Received frames CRC error counter.

MMCRFAECR

Ethernet MMC received frames with alignment error counter register

Offset: 0x98, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RFAEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFAEC
r
Toggle Fields.

RFAEC

Bits 0-31: Received frames alignment error counter.

MMCRGUFCR

MMC received good unicast frames counter register

Offset: 0xC4, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGUFC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGUFC
r
Toggle Fields.

RGUFC

Bits 0-31: Received good unicast frames counter.

Ethernet_PTP

0x40028700: Ethernet: Precision time protocol

6/29 fields covered. Toggle Registers.

PTPTSCR

Ethernet PTP time stamp control register

Offset: 0x0, reset: 0x2000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSPFFMAE
rw
TSCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSSMRME
rw
TSSEME
rw
TSSIPV4FE
rw
TSSIPV6FE
rw
TSSPTPOEFE
rw
TSPTPPSV2E
rw
TSSSR
rw
TSSARFE
rw
TTSARU
rw
TSITE
rw
TSSTU
rw
TSSTI
rw
TSFCU
rw
TSE
rw
Toggle Fields.

TSE

Bit 0: Time stamp enable.

TSFCU

Bit 1: Time stamp fine or coarse update.

TSSTI

Bit 2: Time stamp system time initialize.

TSSTU

Bit 3: Time stamp system time update.

TSITE

Bit 4: Time stamp interrupt trigger enable.

TTSARU

Bit 5: Time stamp addend register update.

TSSARFE

Bit 8: Time stamp snapshot for all received frames enable.

TSSSR

Bit 9: Time stamp subsecond rollover: digital or binary rollover control.

TSPTPPSV2E

Bit 10: Time stamp PTP packet snooping for version2 format enable.

TSSPTPOEFE

Bit 11: Time stamp snapshot for PTP over ethernet frames enable.

TSSIPV6FE

Bit 12: Time stamp snapshot for IPv6 frames enable.

TSSIPV4FE

Bit 13: Time stamp snapshot for IPv4 frames enable.

TSSEME

Bit 14: Time stamp snapshot for event message enable.

TSSMRME

Bit 15: Time stamp snapshot for message relevant to master enable.

TSCNT

Bits 16-17: Time stamp clock node type.

TSPFFMAE

Bit 18: Time stamp PTP frame filtering MAC address enable.

PTPSSIR

Ethernet PTP subsecond increment register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STSSI
rw
Toggle Fields.

STSSI

Bits 0-7: System time subsecond increment.

PTPTSHR

Ethernet PTP time stamp high register

Offset: 0x8, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STS
r
Toggle Fields.

STS

Bits 0-31: System time second.

PTPTSLR

Ethernet PTP time stamp low register

Offset: 0xC, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STPNS
r
STSS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STSS
r
Toggle Fields.

STSS

Bits 0-30: System time subseconds.

STPNS

Bit 31: System time positive or negative sign.

PTPTSHUR

Ethernet PTP time stamp high update register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSUS
rw
Toggle Fields.

TSUS

Bits 0-31: Time stamp update second.

PTPTSLUR

Ethernet PTP time stamp low update register

Offset: 0x14, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSUPNS
rw
TSUSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSUSS
rw
Toggle Fields.

TSUSS

Bits 0-30: Time stamp update subseconds.

TSUPNS

Bit 31: Time stamp update positive or negative sign.

PTPTSAR

Ethernet PTP time stamp addend register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSA
rw
Toggle Fields.

TSA

Bits 0-31: Time stamp addend.

PTPTTHR

Ethernet PTP target time high register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TTSH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTSH
rw
Toggle Fields.

TTSH

Bits 0-31: Target time stamp high.

PTPTTLR

Ethernet PTP target time low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TTSL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTSL
rw
Toggle Fields.

TTSL

Bits 0-31: Target time stamp low.

PTPTSSR

Ethernet PTP time stamp status register

Offset: 0x28, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSTTR
r
TSSO
r
Toggle Fields.

TSSO

Bit 0: Time stamp second overflow.

TSTTR

Bit 1: Time stamp target time reached.

PTPPPSCR

Ethernet PTP PPS control register

Offset: 0x2C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PPSFREQ
r
Toggle Fields.

PPSFREQ

Bits 0-3: PPS frequency selection.

EXTI

0x40013C00: External interrupt/event controller

138/138 fields covered. Toggle Registers.

IMR

Interrupt mask register (EXTI_IMR)

Offset: 0x0, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR22
rw
MR21
rw
MR20
rw
MR19
rw
MR18
rw
MR17
rw
MR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw
MR14
rw
MR13
rw
MR12
rw
MR11
rw
MR10
rw
MR9
rw
MR8
rw
MR7
rw
MR6
rw
MR5
rw
MR4
rw
MR3
rw
MR2
rw
MR1
rw
MR0
rw
Toggle Fields.

MR0

Bit 0: Interrupt Mask on line 0.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Interrupt Mask on line 1.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Interrupt Mask on line 2.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Interrupt Mask on line 3.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Interrupt Mask on line 4.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Interrupt Mask on line 5.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Interrupt Mask on line 6.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Interrupt Mask on line 7.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Interrupt Mask on line 8.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Interrupt Mask on line 9.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Interrupt Mask on line 10.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Interrupt Mask on line 11.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Interrupt Mask on line 12.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Interrupt Mask on line 13.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Interrupt Mask on line 14.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Interrupt Mask on line 15.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: Interrupt Mask on line 16.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: Interrupt Mask on line 17.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR18

Bit 18: Interrupt Mask on line 18.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR19

Bit 19: Interrupt Mask on line 19.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR20

Bit 20: Interrupt Mask on line 20.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR21

Bit 21: Interrupt Mask on line 21.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR22

Bit 22: Interrupt Mask on line 22.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EMR

Event mask register (EXTI_EMR)

Offset: 0x4, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR22
rw
MR21
rw
MR20
rw
MR19
rw
MR18
rw
MR17
rw
MR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw
MR14
rw
MR13
rw
MR12
rw
MR11
rw
MR10
rw
MR9
rw
MR8
rw
MR7
rw
MR6
rw
MR5
rw
MR4
rw
MR3
rw
MR2
rw
MR1
rw
MR0
rw
Toggle Fields.

MR0

Bit 0: Event Mask on line 0.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Event Mask on line 1.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Event Mask on line 2.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Event Mask on line 3.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Event Mask on line 4.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Event Mask on line 5.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Event Mask on line 6.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Event Mask on line 7.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Event Mask on line 8.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Event Mask on line 9.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Event Mask on line 10.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Event Mask on line 11.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Event Mask on line 12.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Event Mask on line 13.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Event Mask on line 14.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Event Mask on line 15.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: Event Mask on line 16.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: Event Mask on line 17.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR18

Bit 18: Event Mask on line 18.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR19

Bit 19: Event Mask on line 19.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR20

Bit 20: Event Mask on line 20.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR21

Bit 21: Event Mask on line 21.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR22

Bit 22: Event Mask on line 22.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

RTSR

Rising Trigger selection register (EXTI_RTSR)

Offset: 0x8, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR22
rw
TR21
rw
TR20
rw
TR19
rw
TR18
rw
TR17
rw
TR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15
rw
TR14
rw
TR13
rw
TR12
rw
TR11
rw
TR10
rw
TR9
rw
TR8
rw
TR7
rw
TR6
rw
TR5
rw
TR4
rw
TR3
rw
TR2
rw
TR1
rw
TR0
rw
Toggle Fields.

TR0

Bit 0: Rising trigger event configuration of line 0.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR1

Bit 1: Rising trigger event configuration of line 1.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR2

Bit 2: Rising trigger event configuration of line 2.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR3

Bit 3: Rising trigger event configuration of line 3.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR4

Bit 4: Rising trigger event configuration of line 4.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR5

Bit 5: Rising trigger event configuration of line 5.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR6

Bit 6: Rising trigger event configuration of line 6.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR7

Bit 7: Rising trigger event configuration of line 7.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR8

Bit 8: Rising trigger event configuration of line 8.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR9

Bit 9: Rising trigger event configuration of line 9.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR10

Bit 10: Rising trigger event configuration of line 10.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR11

Bit 11: Rising trigger event configuration of line 11.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR12

Bit 12: Rising trigger event configuration of line 12.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR13

Bit 13: Rising trigger event configuration of line 13.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR14

Bit 14: Rising trigger event configuration of line 14.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR15

Bit 15: Rising trigger event configuration of line 15.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR16

Bit 16: Rising trigger event configuration of line 16.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR17

Bit 17: Rising trigger event configuration of line 17.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR18

Bit 18: Rising trigger event configuration of line 18.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR19

Bit 19: Rising trigger event configuration of line 19.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR20

Bit 20: Rising trigger event configuration of line 20.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR21

Bit 21: Rising trigger event configuration of line 21.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR22

Bit 22: Rising trigger event configuration of line 22.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTSR

Falling Trigger selection register (EXTI_FTSR)

Offset: 0xC, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR22
rw
TR21
rw
TR20
rw
TR19
rw
TR18
rw
TR17
rw
TR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15
rw
TR14
rw
TR13
rw
TR12
rw
TR11
rw
TR10
rw
TR9
rw
TR8
rw
TR7
rw
TR6
rw
TR5
rw
TR4
rw
TR3
rw
TR2
rw
TR1
rw
TR0
rw
Toggle Fields.

TR0

Bit 0: Falling trigger event configuration of line 0.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR1

Bit 1: Falling trigger event configuration of line 1.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR2

Bit 2: Falling trigger event configuration of line 2.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR3

Bit 3: Falling trigger event configuration of line 3.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR4

Bit 4: Falling trigger event configuration of line 4.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR5

Bit 5: Falling trigger event configuration of line 5.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR6

Bit 6: Falling trigger event configuration of line 6.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR7

Bit 7: Falling trigger event configuration of line 7.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR8

Bit 8: Falling trigger event configuration of line 8.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR9

Bit 9: Falling trigger event configuration of line 9.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR10

Bit 10: Falling trigger event configuration of line 10.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR11

Bit 11: Falling trigger event configuration of line 11.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR12

Bit 12: Falling trigger event configuration of line 12.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR13

Bit 13: Falling trigger event configuration of line 13.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR14

Bit 14: Falling trigger event configuration of line 14.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR15

Bit 15: Falling trigger event configuration of line 15.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR16

Bit 16: Falling trigger event configuration of line 16.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR17

Bit 17: Falling trigger event configuration of line 17.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR18

Bit 18: Falling trigger event configuration of line 18.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR19

Bit 19: Falling trigger event configuration of line 19.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR20

Bit 20: Falling trigger event configuration of line 20.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR21

Bit 21: Falling trigger event configuration of line 21.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR22

Bit 22: Falling trigger event configuration of line 22.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIER

Software interrupt event register (EXTI_SWIER)

Offset: 0x10, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIER22
rw
SWIER21
rw
SWIER20
rw
SWIER19
rw
SWIER18
rw
SWIER17
rw
SWIER16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWIER15
rw
SWIER14
rw
SWIER13
rw
SWIER12
rw
SWIER11
rw
SWIER10
rw
SWIER9
rw
SWIER8
rw
SWIER7
rw
SWIER6
rw
SWIER5
rw
SWIER4
rw
SWIER3
rw
SWIER2
rw
SWIER1
rw
SWIER0
rw
Toggle Fields.

SWIER0

Bit 0: Software Interrupt on line 0.

Allowed values:
1: Pend: Generates an interrupt request

SWIER1

Bit 1: Software Interrupt on line 1.

Allowed values:
1: Pend: Generates an interrupt request

SWIER2

Bit 2: Software Interrupt on line 2.

Allowed values:
1: Pend: Generates an interrupt request

SWIER3

Bit 3: Software Interrupt on line 3.

Allowed values:
1: Pend: Generates an interrupt request

SWIER4

Bit 4: Software Interrupt on line 4.

Allowed values:
1: Pend: Generates an interrupt request

SWIER5

Bit 5: Software Interrupt on line 5.

Allowed values:
1: Pend: Generates an interrupt request

SWIER6

Bit 6: Software Interrupt on line 6.

Allowed values:
1: Pend: Generates an interrupt request

SWIER7

Bit 7: Software Interrupt on line 7.

Allowed values:
1: Pend: Generates an interrupt request

SWIER8

Bit 8: Software Interrupt on line 8.

Allowed values:
1: Pend: Generates an interrupt request

SWIER9

Bit 9: Software Interrupt on line 9.

Allowed values:
1: Pend: Generates an interrupt request

SWIER10

Bit 10: Software Interrupt on line 10.

Allowed values:
1: Pend: Generates an interrupt request

SWIER11

Bit 11: Software Interrupt on line 11.

Allowed values:
1: Pend: Generates an interrupt request

SWIER12

Bit 12: Software Interrupt on line 12.

Allowed values:
1: Pend: Generates an interrupt request

SWIER13

Bit 13: Software Interrupt on line 13.

Allowed values:
1: Pend: Generates an interrupt request

SWIER14

Bit 14: Software Interrupt on line 14.

Allowed values:
1: Pend: Generates an interrupt request

SWIER15

Bit 15: Software Interrupt on line 15.

Allowed values:
1: Pend: Generates an interrupt request

SWIER16

Bit 16: Software Interrupt on line 16.

Allowed values:
1: Pend: Generates an interrupt request

SWIER17

Bit 17: Software Interrupt on line 17.

Allowed values:
1: Pend: Generates an interrupt request

SWIER18

Bit 18: Software Interrupt on line 18.

Allowed values:
1: Pend: Generates an interrupt request

SWIER19

Bit 19: Software Interrupt on line 19.

Allowed values:
1: Pend: Generates an interrupt request

SWIER20

Bit 20: Software Interrupt on line 20.

Allowed values:
1: Pend: Generates an interrupt request

SWIER21

Bit 21: Software Interrupt on line 21.

Allowed values:
1: Pend: Generates an interrupt request

SWIER22

Bit 22: Software Interrupt on line 22.

Allowed values:
1: Pend: Generates an interrupt request

PR

Pending register (EXTI_PR)

Offset: 0x14, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PR22
rw
PR21
rw
PR20
rw
PR19
rw
PR18
rw
PR17
rw
PR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR15
rw
PR14
rw
PR13
rw
PR12
rw
PR11
rw
PR10
rw
PR9
rw
PR8
rw
PR7
rw
PR6
rw
PR5
rw
PR4
rw
PR3
rw
PR2
rw
PR1
rw
PR0
rw
Toggle Fields.

PR0

Bit 0: Pending bit 0.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR1

Bit 1: Pending bit 1.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR2

Bit 2: Pending bit 2.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR3

Bit 3: Pending bit 3.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR4

Bit 4: Pending bit 4.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR5

Bit 5: Pending bit 5.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR6

Bit 6: Pending bit 6.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR7

Bit 7: Pending bit 7.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR8

Bit 8: Pending bit 8.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR9

Bit 9: Pending bit 9.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR10

Bit 10: Pending bit 10.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR11

Bit 11: Pending bit 11.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR12

Bit 12: Pending bit 12.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR13

Bit 13: Pending bit 13.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR14

Bit 14: Pending bit 14.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR15

Bit 15: Pending bit 15.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR16

Bit 16: Pending bit 16.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR17

Bit 17: Pending bit 17.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR18

Bit 18: Pending bit 18.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR19

Bit 19: Pending bit 19.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR20

Bit 20: Pending bit 20.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR21

Bit 21: Pending bit 21.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR22

Bit 22: Pending bit 22.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FLASH

0x40023C00: FLASH

1/32 fields covered. Toggle Registers.

ACR

Flash access control register

Offset: 0x0, reset: 0x00000000, access: Unspecified

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCRST
rw
ICRST
w
DCEN
rw
ICEN
rw
PRFTEN
rw
LATENCY
rw
Toggle Fields.

LATENCY

Bits 0-2: Latency.

PRFTEN

Bit 8: Prefetch enable.

ICEN

Bit 9: Instruction cache enable.

DCEN

Bit 10: Data cache enable.

ICRST

Bit 11: Instruction cache reset.

DCRST

Bit 12: Data cache reset.

KEYR

Flash key register

Offset: 0x4, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-31: FPEC key.

OPTKEYR

Flash option key register

Offset: 0x8, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEY
w
Toggle Fields.

OPTKEY

Bits 0-31: Option byte key.

SR

Status register

Offset: 0xC, reset: 0x00000000, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PGSERR
rw
PGPERR
rw
PGAERR
rw
WRPERR
rw
OPERR
rw
EOP
rw
Toggle Fields.

EOP

Bit 0: End of operation.

OPERR

Bit 1: Operation error.

WRPERR

Bit 4: Write protection error.

PGAERR

Bit 5: Programming alignment error.

PGPERR

Bit 6: Programming parallelism error.

PGSERR

Bit 7: Programming sequence error.

BSY

Bit 16: Busy.

CR

Control register

Offset: 0x10, reset: 0x80000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
ERRIE
rw
EOPIE
rw
STRT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSIZE
rw
SNB
rw
MER
rw
SER
rw
PG
rw
Toggle Fields.

PG

Bit 0: Programming.

SER

Bit 1: Sector Erase.

MER

Bit 2: Mass Erase.

SNB

Bits 3-6: Sector number.

PSIZE

Bits 8-9: Program size.

STRT

Bit 16: Start.

EOPIE

Bit 24: End of operation interrupt enable.

ERRIE

Bit 25: Error interrupt enable.

LOCK

Bit 31: Lock.

OPTCR

Flash option control register

Offset: 0x14, reset: 0x00000014, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
nWRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDP
rw
nRST_STDBY
rw
nRST_STOP
rw
WDG_SW
rw
BOR_LEV
rw
OPTSTRT
rw
OPTLOCK
rw
Toggle Fields.

OPTLOCK

Bit 0: Option lock.

OPTSTRT

Bit 1: Option start.

BOR_LEV

Bits 2-3: BOR reset Level.

WDG_SW

Bit 5: WDG_SW User option bytes.

nRST_STOP

Bit 6: nRST_STOP User option bytes.

nRST_STDBY

Bit 7: nRST_STDBY User option bytes.

RDP

Bits 8-15: Read protect.

nWRP

Bits 16-27: Not write protect.

FSMC

0xA0000000: Flexible static memory controller

81/89 fields covered. Toggle Registers.

BCR1

SRAM/NOR-Flash chip-select control register 1

Offset: 0x0, reset: 0x000030D0, access: read-write

14/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBURSTRW
rw
CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw
EXTMOD
rw
WAITEN
rw
WREN
rw
WAITCFG
rw
WRAPMOD
rw
WAITPOL
rw
BURSTEN
rw
FACCEN
rw
MWID
rw
MTYP
rw
MUXEN
rw
MBKEN
rw
Toggle Fields.

MBKEN

Bit 0: MBKEN.

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: MUXEN.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: MTYP.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: MWID.

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: FACCEN.

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: BURSTEN.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: WAITPOL.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: WREN.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: WAITEN.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: EXTMOD.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: ASYNCWAIT.

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM page size.

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: CBURSTRW.

Allowed values:
1: Enabled: Write operations are performed in synchronous mode
0: Disabled: Write operations are always performed in asynchronous mode

BTR%s

SRAM/NOR-Flash chip-select timing register 1

Offset: 0x4, reset: 0xFFFFFFFF, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
DATLAT
rw
CLKDIV
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle Fields.

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0-15

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 1-15

DATAST

Bits 8-15: DATAST.

Allowed values: 1-255

BUSTURN

Bits 16-19: BUSTURN.

Allowed values: 0-15

CLKDIV

Bits 20-23: CLKDIV.

Allowed values: 1-15

DATLAT

Bits 24-27: DATLAT.

Allowed values: 0-15

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BCR%s

SRAM/NOR-Flash chip-select control register 2

Offset: 0x8, reset: 0x000030D0, access: read-write

14/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBURSTRW
rw
CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw
EXTMOD
rw
WAITEN
rw
WREN
rw
WAITCFG
rw
WRAPMOD
rw
WAITPOL
rw
BURSTEN
rw
FACCEN
rw
MWID
rw
MTYP
rw
MUXEN
rw
MBKEN
rw
Toggle Fields.

MBKEN

Bit 0: MBKEN.

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: MUXEN.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: MTYP.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: MWID.

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: FACCEN.

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: BURSTEN.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: WAITPOL.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WRAPMOD

Bit 10: WRAPMOD.

WAITCFG

Bit 11: WAITCFG.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: WREN.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: WAITEN.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: EXTMOD.

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: ASYNCWAIT.

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM page size.

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: CBURSTRW.

Allowed values:
1: Enabled: Write operations are performed in synchronous mode
0: Disabled: Write operations are always performed in asynchronous mode

PCR%s

PC Card/NAND Flash control register 2

Offset: 0x60, reset: 0x00000018, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCPS
rw
TAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAR
rw
TCLR
rw
ECCEN
rw
PWID
rw
PTYP
rw
PBKEN
rw
PWAITEN
rw
Toggle Fields.

PWAITEN

Bit 1: PWAITEN.

Allowed values:
0: Disabled: Wait feature disabled
1: Enabled: Wait feature enabled

PBKEN

Bit 2: PBKEN.

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

PTYP

Bit 3: PTYP.

Allowed values:
1: NANDFlash: NAND Flash

PWID

Bits 4-5: PWID.

Allowed values:
0: Bits8: External memory device width 8 bits
1: Bits16: External memory device width 16 bits

ECCEN

Bit 6: ECCEN.

Allowed values:
0: Disabled: ECC logic is disabled and reset
1: Enabled: ECC logic is enabled

TCLR

Bits 9-12: TCLR.

Allowed values: 0-15

TAR

Bits 13-16: TAR.

Allowed values: 0-15

ECCPS

Bits 17-19: ECCPS.

Allowed values:
0: Bytes256: ECC page size 256 bytes
1: Bytes512: ECC page size 512 bytes
2: Bytes1024: ECC page size 1024 bytes
3: Bytes2048: ECC page size 2048 bytes
4: Bytes4096: ECC page size 4096 bytes
5: Bytes8192: ECC page size 8192 bytes

SR%s

FIFO status and interrupt register 2

Offset: 0x64, reset: 0x00000040, access: Unspecified

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEMPT
r
IFEN
rw
ILEN
rw
IREN
rw
IFS
rw
ILS
rw
IRS
rw
Toggle Fields.

IRS

Bit 0: IRS.

Allowed values:
0: DidNotOccur: Interrupt rising edge did not occur
1: Occurred: Interrupt rising edge occurred

ILS

Bit 1: ILS.

Allowed values:
0: DidNotOccur: Interrupt high-level did not occur
1: Occurred: Interrupt high-level occurred

IFS

Bit 2: IFS.

Allowed values:
0: DidNotOccur: Interrupt falling edge did not occur
1: Occurred: Interrupt falling edge occurred

IREN

Bit 3: IREN.

Allowed values:
0: Disabled: Interrupt rising edge detection request disabled
1: Enabled: Interrupt rising edge detection request enabled

ILEN

Bit 4: ILEN.

Allowed values:
0: Disabled: Interrupt high-level detection request disabled
1: Enabled: Interrupt high-level detection request enabled

IFEN

Bit 5: IFEN.

Allowed values:
0: Disabled: Interrupt falling edge detection request disabled
1: Enabled: Interrupt falling edge detection request enabled

FEMPT

Bit 6: FEMPT.

Allowed values:
0: NotEmpty: FIFO not empty
1: Empty: FIFO empty

PMEM2

Common memory space timing register 2

Offset: 0x68, reset: 0xFCFCFCFC, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZ
rw
MEMHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAIT
rw
MEMSET
rw
Toggle Fields.

MEMSET

Bits 0-7: MEMSETx.

Allowed values: 0-254

MEMWAIT

Bits 8-15: MEMWAITx.

Allowed values: 1-254

MEMHOLD

Bits 16-23: MEMHOLDx.

Allowed values: 1-254

MEMHIZ

Bits 24-31: MEMHIZx.

Allowed values: 0-254

PATT2

Attribute memory space timing register 2

Offset: 0x6C, reset: 0xFCFCFCFC, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw
ATTHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw
ATTSET
rw
Toggle Fields.

ATTSET

Bits 0-7: Attribute memory x setup time.

Allowed values: 0-254

ATTWAIT

Bits 8-15: Attribute memory x wait time.

Allowed values: 1-254

ATTHOLD

Bits 16-23: Attribute memory x hold time.

Allowed values: 1-254

ATTHIZ

Bits 24-31: Attribute memory x databus HiZ time.

Allowed values: 0-254

ECCR2

ECC result register 2

Offset: 0x74, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC
r
Toggle Fields.

ECC

Bits 0-31: ECC result.

Allowed values: 0-4294967295

PMEM3

Common memory space timing register 3

Offset: 0x88, reset: 0xFCFCFCFC, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZ
rw
MEMHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAIT
rw
MEMSET
rw
Toggle Fields.

MEMSET

Bits 0-7: MEMSETx.

Allowed values: 0-254

MEMWAIT

Bits 8-15: MEMWAITx.

Allowed values: 1-254

MEMHOLD

Bits 16-23: MEMHOLDx.

Allowed values: 1-254

MEMHIZ

Bits 24-31: MEMHIZx.

Allowed values: 0-254

PATT3

Attribute memory space timing register 3

Offset: 0x8C, reset: 0xFCFCFCFC, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw
ATTHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw
ATTSET
rw
Toggle Fields.

ATTSET

Bits 0-7: ATTSETx.

Allowed values: 0-254

ATTWAIT

Bits 8-15: ATTWAITx.

Allowed values: 1-254

ATTHOLD

Bits 16-23: ATTHOLDx.

Allowed values: 1-254

ATTHIZ

Bits 24-31: ATTHIZx.

Allowed values: 0-254

ECCR3

ECC result register 3

Offset: 0x94, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC
r
Toggle Fields.

ECC

Bits 0-31: ECCx.

Allowed values: 0-4294967295

PMEM4

Common memory space timing register 4

Offset: 0xA8, reset: 0xFCFCFCFC, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZ
rw
MEMHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAIT
rw
MEMSET
rw
Toggle Fields.

MEMSET

Bits 0-7: MEMSETx.

Allowed values: 0-254

MEMWAIT

Bits 8-15: MEMWAITx.

Allowed values: 1-254

MEMHOLD

Bits 16-23: MEMHOLDx.

Allowed values: 1-254

MEMHIZ

Bits 24-31: MEMHIZx.

Allowed values: 0-254

PATT4

Attribute memory space timing register 4

Offset: 0xAC, reset: 0xFCFCFCFC, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw
ATTHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw
ATTSET
rw
Toggle Fields.

ATTSET

Bits 0-7: ATTSETx.

Allowed values: 0-254

ATTWAIT

Bits 8-15: ATTWAITx.

Allowed values: 1-254

ATTHOLD

Bits 16-23: ATTHOLDx.

Allowed values: 1-254

ATTHIZ

Bits 24-31: ATTHIZx.

Allowed values: 0-254

PIO4

I/O space timing register 4

Offset: 0xB0, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOHIZx
rw
IOHOLDx
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOWAITx
rw
IOSETx
rw
Toggle Fields.

IOSETx

Bits 0-7: IOSETx.

IOWAITx

Bits 8-15: IOWAITx.

IOHOLDx

Bits 16-23: IOHOLDx.

IOHIZx

Bits 24-31: IOHIZx.

BWTR%s

SRAM/NOR-Flash write timing registers 1

Offset: 0x104, reset: 0x0FFFFFFF, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
DATLAT
rw
CLKDIV
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle Fields.

ADDSET

Bits 0-3: ADDSET.

Allowed values: 0-15

ADDHLD

Bits 4-7: ADDHLD.

Allowed values: 1-15

DATAST

Bits 8-15: DATAST.

Allowed values: 1-255

BUSTURN

Bits 16-19: Bus turnaround phase duration.

Allowed values: 0-15

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

GPIOA

0x40020000: General-purpose I/Os

161/161 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0xA8000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x64000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw
AFRL6
rw
AFRL5
rw
AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw
AFRL2
rw
AFRL1
rw
AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw
AFRH14
rw
AFRH13
rw
AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw
AFRH10
rw
AFRH9
rw
AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOB

0x40020400: General-purpose I/Os

161/161 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0x00000280, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x000000C0, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000100, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw
AFRL6
rw
AFRL5
rw
AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw
AFRL2
rw
AFRL1
rw
AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw
AFRH14
rw
AFRH13
rw
AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw
AFRH10
rw
AFRH9
rw
AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOC

0x40020800: General-purpose I/Os

161/161 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bit 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bit 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bit 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bit 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bit 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bit 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bit 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bit 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bit 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bit 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bit 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bit 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bit 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bit 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bit 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bit 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw
AFRL6
rw
AFRL5
rw
AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw
AFRL2
rw
AFRL1
rw
AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw
AFRH14
rw
AFRH13
rw
AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw
AFRH10
rw
AFRH9
rw
AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOD

0X40020C00: General-purpose I/Os

161/161 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bit 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bit 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bit 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bit 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bit 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bit 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bit 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bit 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bit 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bit 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bit 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bit 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bit 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bit 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bit 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bit 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw
AFRL6
rw
AFRL5
rw
AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw
AFRL2
rw
AFRL1
rw
AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw
AFRH14
rw
AFRH13
rw
AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw
AFRH10
rw
AFRH9
rw
AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOE

0x40021000: General-purpose I/Os

161/161 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bit 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bit 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bit 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bit 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bit 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bit 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bit 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bit 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bit 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bit 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bit 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bit 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bit 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bit 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bit 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bit 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw
AFRL6
rw
AFRL5
rw
AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw
AFRL2
rw
AFRL1
rw
AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw
AFRH14
rw
AFRH13
rw
AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw
AFRH10
rw
AFRH9
rw
AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOF

0x40021400: General-purpose I/Os

161/161 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bit 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bit 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bit 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bit 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bit 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bit 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bit 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bit 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bit 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bit 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bit 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bit 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bit 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bit 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bit 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bit 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw
AFRL6
rw
AFRL5
rw
AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw
AFRL2
rw
AFRL1
rw
AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw
AFRH14
rw
AFRH13
rw
AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw
AFRH10
rw
AFRH9
rw
AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOG

0x40021800: General-purpose I/Os

161/161 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bit 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bit 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bit 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bit 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bit 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bit 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bit 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bit 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bit 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bit 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bit 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bit 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bit 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bit 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bit 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bit 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw
AFRL6
rw
AFRL5
rw
AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw
AFRL2
rw
AFRL1
rw
AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw
AFRH14
rw
AFRH13
rw
AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw
AFRH10
rw
AFRH9
rw
AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOH

0x40021C00: General-purpose I/Os

161/161 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bit 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bit 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bit 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bit 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bit 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bit 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bit 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bit 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bit 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bit 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bit 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bit 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bit 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bit 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bit 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bit 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw
AFRL6
rw
AFRL5
rw
AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw
AFRL2
rw
AFRL1
rw
AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw
AFRH14
rw
AFRH13
rw
AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw
AFRH10
rw
AFRH9
rw
AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOI

0x40022000: General-purpose I/Os

161/161 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bit 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bit 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bit 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bit 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bit 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bit 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bit 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bit 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bit 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bit 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bit 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bit 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bit 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bit 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bit 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bit 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw
AFRL6
rw
AFRL5
rw
AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw
AFRL2
rw
AFRL1
rw
AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw
AFRH14
rw
AFRH13
rw
AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw
AFRH10
rw
AFRH9
rw
AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

HASH

0x50060400: Hash processor

5/19 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: Unspecified

2/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DINNE
r
NBW
r
ALGO
rw
MODE
rw
DATATYPE
rw
DMAE
rw
INIT
w
Toggle Fields.

INIT

Bit 2: Initialize message digest calculation.

DMAE

Bit 3: DMA enable.

DATATYPE

Bits 4-5: Data type selection.

MODE

Bit 6: Mode selection.

ALGO

Bit 7: Algorithm selection.

NBW

Bits 8-11: Number of words already pushed.

DINNE

Bit 12: DIN not empty.

LKEY

Bit 16: Long key selection.

DIN

data input register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN
rw
Toggle Fields.

DATAIN

Bits 0-31: Data input.

STR

start register

Offset: 0x8, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCAL
w
NBLW
w
Toggle Fields.

NBLW

Bits 0-4: Number of valid bits in the last word of the message.

DCAL

Bit 8: Digest calculation.

HR%s

digest registers

Offset: 0xC, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H
r
Toggle Fields.

H

Bits 0-31: H0.

IMR

interrupt enable register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCIE
rw
DINIE
rw
Toggle Fields.

DINIE

Bit 0: Data input interrupt enable.

DCIE

Bit 1: Digest calculation completion interrupt enable.

SR

status register

Offset: 0x24, reset: 0x00000001, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
DMAS
r
DCIS
rw
DINIS
rw
Toggle Fields.

DINIS

Bit 0: Data input interrupt status.

DCIS

Bit 1: Digest calculation completion interrupt status.

DMAS

Bit 2: DMA Status.

BUSY

Bit 3: Busy bit.

CSR%s

context swap registers

Offset: 0xF8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR
rw
Toggle Fields.

CSR

Bits 0-31: CSR0.

I2C1

0x40005400: Inter-integrated circuit

51/51 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
rw
ALERT
rw
PEC
rw
POS
rw
ACK
rw
STOP
rw
START
rw
NOSTRETCH
rw
ENGC
rw
ENPEC
rw
ENARP
rw
SMBTYPE
rw
SMBUS
rw
PE
rw
Toggle Fields.

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBUS

Bit 1: SMBus mode.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBTYPE

Bit 3: SMBus type.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ENARP

Bit 4: ARP enable.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

ENPEC

Bit 5: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

ENGC

Bit 6: General call enable.

Allowed values:
0: Disabled: General call disabled
1: Enabled: General call enabled

NOSTRETCH

Bit 7: Clock stretching disable (Slave mode).

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: In master mode: repeated start generation, in slave mode: start generation when bus is free

STOP

Bit 9: Stop generation.

Allowed values:
0: NoStop: No Stop generation
1: Stop: In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte

ACK

Bit 10: Acknowledge enable.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POS

Bit 11: Acknowledge/PEC Position (for data reception).

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PEC

Bit 12: Packet error checking.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

ALERT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SWRST

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAST
rw
DMAEN
rw
ITBUFEN
rw
ITEVTEN
rw
ITERREN
rw
FREQ
rw
Toggle Fields.

FREQ

Bits 0-5: Peripheral clock frequency.

Allowed values: 2-50

ITERREN

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

ITEVTEN

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

ITBUFEN

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TxE=1 or RxNE=1 does not generate any interrupt
1: Enabled: TxE=1 or RxNE=1 generates Event interrupt

DMAEN

Bit 11: DMA requests enable.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA request enabled when TxE=1 or RxNE=1

LAST

Bit 12: DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

OAR1

Own address register 1

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDMODE
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-9: Interface address.

Allowed values: 0-1023

ADDMODE

Bit 15: Addressing mode (slave mode).

Allowed values:
0: ADD7: 7-bit slave address
1: ADD10: 10-bit slave address

OAR2

Own address register 2

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD2
rw
ENDUAL
rw
Toggle Fields.

ENDUAL

Bit 0: Dual addressing mode enable.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADD2

Bits 1-7: Interface address.

Allowed values: 0-127

DR

Data register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-7: 8-bit data register.

Allowed values: 0-255

SR1

Status register 1

Offset: 0x14, reset: 0x0000, access: Unspecified

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALERT
rw
TIMEOUT
rw
PECERR
rw
OVR
rw
AF
rw
ARLO
rw
BERR
rw
TxE
r
RxNE
r
STOPF
r
ADD10
r
BTF
r
ADDR
r
SB
r
Toggle Fields.

SB

Bit 0: Start bit (Master mode).

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDR

Bit 1: Address sent (master mode)/matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTF

Bit 2: Byte transfer finished.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10

Bit 3: 10-bit header sent (Master mode).

STOPF

Bit 4: Stop detection (slave mode).

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RxNE

Bit 6: Data register not empty (receivers).

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty

TxE

Bit 7: Data register empty (transmitters).

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

ARLO

Bit 9: Arbitration lost (master mode).

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AF

Bit 10: Acknowledge failure.

Allowed values:
0: NoFailure: No acknowledge failure
1: Failure: Acknowledge failure

OVR

Bit 11: Overrun/Underrun.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC Error in reception.

Allowed values:
0: NoError: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
1: Error: PEC error: receiver returns NACK after PEC reception (whatever ACK)

TIMEOUT

Bit 14: Timeout or Tlow error.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained LOW for 25 ms

SMBALERT

Bit 15: SMBus alert.

Allowed values:
0: NoAlert: No SMBALERT occured
1: Alert: SMBALERT occurred

SR2

Status register 2

Offset: 0x18, reset: 0x0000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
DUALF
r
SMBHOST
r
SMBDEFAULT
r
GENCALL
r
TRA
r
BUSY
r
MSL
r
Toggle Fields.

MSL

Bit 0: Master/slave.

BUSY

Bit 1: Bus busy.

TRA

Bit 2: Transmitter/receiver.

GENCALL

Bit 4: General call address (Slave mode).

SMBDEFAULT

Bit 5: SMBus device default address (Slave mode).

SMBHOST

Bit 6: SMBus host header (Slave mode).

DUALF

Bit 7: Dual flag (Slave mode).

PEC

Bits 8-15: acket error checking register.

CCR

Clock control register

Offset: 0x1C, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F_S
rw
DUTY
rw
CCR
rw
Toggle Fields.

CCR

Bits 0-11: Clock control register in Fast/Standard mode (Master mode).

Allowed values: 1-4095

DUTY

Bit 14: Fast mode duty cycle.

Allowed values:
0: Duty2_1: Duty cycle t_low/t_high = 2/1
1: Duty16_9: Duty cycle t_low/t_high = 16/9

F_S

Bit 15: I2C master mode selection.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

TRISE

TRISE register

Offset: 0x20, reset: 0x0002, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRISE
rw
Toggle Fields.

TRISE

Bits 0-5: Maximum rise time in Fast/Standard mode (Master mode).

Allowed values: 0-63

I2C2

0x40005800: Inter-integrated circuit

51/51 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
rw
ALERT
rw
PEC
rw
POS
rw
ACK
rw
STOP
rw
START
rw
NOSTRETCH
rw
ENGC
rw
ENPEC
rw
ENARP
rw
SMBTYPE
rw
SMBUS
rw
PE
rw
Toggle Fields.

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBUS

Bit 1: SMBus mode.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBTYPE

Bit 3: SMBus type.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ENARP

Bit 4: ARP enable.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

ENPEC

Bit 5: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

ENGC

Bit 6: General call enable.

Allowed values:
0: Disabled: General call disabled
1: Enabled: General call enabled

NOSTRETCH

Bit 7: Clock stretching disable (Slave mode).

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: In master mode: repeated start generation, in slave mode: start generation when bus is free

STOP

Bit 9: Stop generation.

Allowed values:
0: NoStop: No Stop generation
1: Stop: In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte

ACK

Bit 10: Acknowledge enable.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POS

Bit 11: Acknowledge/PEC Position (for data reception).

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PEC

Bit 12: Packet error checking.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

ALERT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SWRST

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAST
rw
DMAEN
rw
ITBUFEN
rw
ITEVTEN
rw
ITERREN
rw
FREQ
rw
Toggle Fields.

FREQ

Bits 0-5: Peripheral clock frequency.

Allowed values: 2-50

ITERREN

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

ITEVTEN

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

ITBUFEN

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TxE=1 or RxNE=1 does not generate any interrupt
1: Enabled: TxE=1 or RxNE=1 generates Event interrupt

DMAEN

Bit 11: DMA requests enable.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA request enabled when TxE=1 or RxNE=1

LAST

Bit 12: DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

OAR1

Own address register 1

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDMODE
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-9: Interface address.

Allowed values: 0-1023

ADDMODE

Bit 15: Addressing mode (slave mode).

Allowed values:
0: ADD7: 7-bit slave address
1: ADD10: 10-bit slave address

OAR2

Own address register 2

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD2
rw
ENDUAL
rw
Toggle Fields.

ENDUAL

Bit 0: Dual addressing mode enable.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADD2

Bits 1-7: Interface address.

Allowed values: 0-127

DR

Data register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-7: 8-bit data register.

Allowed values: 0-255

SR1

Status register 1

Offset: 0x14, reset: 0x0000, access: Unspecified

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALERT
rw
TIMEOUT
rw
PECERR
rw
OVR
rw
AF
rw
ARLO
rw
BERR
rw
TxE
r
RxNE
r
STOPF
r
ADD10
r
BTF
r
ADDR
r
SB
r
Toggle Fields.

SB

Bit 0: Start bit (Master mode).

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDR

Bit 1: Address sent (master mode)/matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTF

Bit 2: Byte transfer finished.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10

Bit 3: 10-bit header sent (Master mode).

STOPF

Bit 4: Stop detection (slave mode).

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RxNE

Bit 6: Data register not empty (receivers).

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty

TxE

Bit 7: Data register empty (transmitters).

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

ARLO

Bit 9: Arbitration lost (master mode).

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AF

Bit 10: Acknowledge failure.

Allowed values:
0: NoFailure: No acknowledge failure
1: Failure: Acknowledge failure

OVR

Bit 11: Overrun/Underrun.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC Error in reception.

Allowed values:
0: NoError: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
1: Error: PEC error: receiver returns NACK after PEC reception (whatever ACK)

TIMEOUT

Bit 14: Timeout or Tlow error.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained LOW for 25 ms

SMBALERT

Bit 15: SMBus alert.

Allowed values:
0: NoAlert: No SMBALERT occured
1: Alert: SMBALERT occurred

SR2

Status register 2

Offset: 0x18, reset: 0x0000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
DUALF
r
SMBHOST
r
SMBDEFAULT
r
GENCALL
r
TRA
r
BUSY
r
MSL
r
Toggle Fields.

MSL

Bit 0: Master/slave.

BUSY

Bit 1: Bus busy.

TRA

Bit 2: Transmitter/receiver.

GENCALL

Bit 4: General call address (Slave mode).

SMBDEFAULT

Bit 5: SMBus device default address (Slave mode).

SMBHOST

Bit 6: SMBus host header (Slave mode).

DUALF

Bit 7: Dual flag (Slave mode).

PEC

Bits 8-15: acket error checking register.

CCR

Clock control register

Offset: 0x1C, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F_S
rw
DUTY
rw
CCR
rw
Toggle Fields.

CCR

Bits 0-11: Clock control register in Fast/Standard mode (Master mode).

Allowed values: 1-4095

DUTY

Bit 14: Fast mode duty cycle.

Allowed values:
0: Duty2_1: Duty cycle t_low/t_high = 2/1
1: Duty16_9: Duty cycle t_low/t_high = 16/9

F_S

Bit 15: I2C master mode selection.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

TRISE

TRISE register

Offset: 0x20, reset: 0x0002, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRISE
rw
Toggle Fields.

TRISE

Bits 0-5: Maximum rise time in Fast/Standard mode (Master mode).

Allowed values: 0-63

I2C3

0x40005C00: Inter-integrated circuit

51/51 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
rw
ALERT
rw
PEC
rw
POS
rw
ACK
rw
STOP
rw
START
rw
NOSTRETCH
rw
ENGC
rw
ENPEC
rw
ENARP
rw
SMBTYPE
rw
SMBUS
rw
PE
rw
Toggle Fields.

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBUS

Bit 1: SMBus mode.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBTYPE

Bit 3: SMBus type.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ENARP

Bit 4: ARP enable.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

ENPEC

Bit 5: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

ENGC

Bit 6: General call enable.

Allowed values:
0: Disabled: General call disabled
1: Enabled: General call enabled

NOSTRETCH

Bit 7: Clock stretching disable (Slave mode).

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: In master mode: repeated start generation, in slave mode: start generation when bus is free

STOP

Bit 9: Stop generation.

Allowed values:
0: NoStop: No Stop generation
1: Stop: In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte

ACK

Bit 10: Acknowledge enable.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POS

Bit 11: Acknowledge/PEC Position (for data reception).

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PEC

Bit 12: Packet error checking.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

ALERT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SWRST

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAST
rw
DMAEN
rw
ITBUFEN
rw
ITEVTEN
rw
ITERREN
rw
FREQ
rw
Toggle Fields.

FREQ

Bits 0-5: Peripheral clock frequency.

Allowed values: 2-50

ITERREN

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

ITEVTEN

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

ITBUFEN

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TxE=1 or RxNE=1 does not generate any interrupt
1: Enabled: TxE=1 or RxNE=1 generates Event interrupt

DMAEN

Bit 11: DMA requests enable.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA request enabled when TxE=1 or RxNE=1

LAST

Bit 12: DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

OAR1

Own address register 1

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDMODE
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-9: Interface address.

Allowed values: 0-1023

ADDMODE

Bit 15: Addressing mode (slave mode).

Allowed values:
0: ADD7: 7-bit slave address
1: ADD10: 10-bit slave address

OAR2

Own address register 2

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD2
rw
ENDUAL
rw
Toggle Fields.

ENDUAL

Bit 0: Dual addressing mode enable.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADD2

Bits 1-7: Interface address.

Allowed values: 0-127

DR

Data register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-7: 8-bit data register.

Allowed values: 0-255

SR1

Status register 1

Offset: 0x14, reset: 0x0000, access: Unspecified

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALERT
rw
TIMEOUT
rw
PECERR
rw
OVR
rw
AF
rw
ARLO
rw
BERR
rw
TxE
r
RxNE
r
STOPF
r
ADD10
r
BTF
r
ADDR
r
SB
r
Toggle Fields.

SB

Bit 0: Start bit (Master mode).

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDR

Bit 1: Address sent (master mode)/matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTF

Bit 2: Byte transfer finished.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10

Bit 3: 10-bit header sent (Master mode).

STOPF

Bit 4: Stop detection (slave mode).

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RxNE

Bit 6: Data register not empty (receivers).

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty

TxE

Bit 7: Data register empty (transmitters).

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

ARLO

Bit 9: Arbitration lost (master mode).

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AF

Bit 10: Acknowledge failure.

Allowed values:
0: NoFailure: No acknowledge failure
1: Failure: Acknowledge failure

OVR

Bit 11: Overrun/Underrun.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC Error in reception.

Allowed values:
0: NoError: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
1: Error: PEC error: receiver returns NACK after PEC reception (whatever ACK)

TIMEOUT

Bit 14: Timeout or Tlow error.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained LOW for 25 ms

SMBALERT

Bit 15: SMBus alert.

Allowed values:
0: NoAlert: No SMBALERT occured
1: Alert: SMBALERT occurred

SR2

Status register 2

Offset: 0x18, reset: 0x0000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
DUALF
r
SMBHOST
r
SMBDEFAULT
r
GENCALL
r
TRA
r
BUSY
r
MSL
r
Toggle Fields.

MSL

Bit 0: Master/slave.

BUSY

Bit 1: Bus busy.

TRA

Bit 2: Transmitter/receiver.

GENCALL

Bit 4: General call address (Slave mode).

SMBDEFAULT

Bit 5: SMBus device default address (Slave mode).

SMBHOST

Bit 6: SMBus host header (Slave mode).

DUALF

Bit 7: Dual flag (Slave mode).

PEC

Bits 8-15: acket error checking register.

CCR

Clock control register

Offset: 0x1C, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F_S
rw
DUTY
rw
CCR
rw
Toggle Fields.

CCR

Bits 0-11: Clock control register in Fast/Standard mode (Master mode).

Allowed values: 1-4095

DUTY

Bit 14: Fast mode duty cycle.

Allowed values:
0: Duty2_1: Duty cycle t_low/t_high = 2/1
1: Duty16_9: Duty cycle t_low/t_high = 16/9

F_S

Bit 15: I2C master mode selection.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

TRISE

TRISE register

Offset: 0x20, reset: 0x0002, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRISE
rw
Toggle Fields.

TRISE

Bits 0-5: Maximum rise time in Fast/Standard mode (Master mode).

Allowed values: 0-63

IWDG

0x40003000: Independent watchdog

5/5 fields covered. Toggle Registers.

KR

Key register

Offset: 0x0, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-15: Key value (write only, read 0000h).

Allowed values:
21845: Enable: Enable access to PR, RLR and WINR registers (0x5555)
43690: Reset: Reset the watchdog value (0xAAAA)
52428: Start: Start the watchdog (0xCCCC)

PR

Prescaler register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle Fields.

PR

Bits 0-2: Prescaler divider.

Allowed values:
0: DivideBy4: Divider /4
1: DivideBy8: Divider /8
2: DivideBy16: Divider /16
3: DivideBy32: Divider /32
4: DivideBy64: Divider /64
5: DivideBy128: Divider /128
6: DivideBy256: Divider /256
7: DivideBy256bis: Divider /256

RLR

Reload register

Offset: 0x8, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle Fields.

RL

Bits 0-11: Watchdog counter reload value.

Allowed values: 0-4095

SR

Status register

Offset: 0xC, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RVU
r
PVU
r
Toggle Fields.

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

MPU

0xE000ED90: Memory protection unit

6/19 fields covered. Toggle Registers.

MPU_TYPER

MPU type register

Offset: 0x0, reset: 0X00000800, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IREGION
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DREGION
r
SEPARATE
r
Toggle Fields.

SEPARATE

Bit 0: Separate flag.

DREGION

Bits 8-15: Number of MPU data regions.

IREGION

Bits 16-23: Number of MPU instruction regions.

MPU_CTRL

MPU control register

Offset: 0x4, reset: 0X00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIVDEFENA
r
HFNMIENA
r
ENABLE
r
Toggle Fields.

ENABLE

Bit 0: Enables the MPU.

HFNMIENA

Bit 1: Enables the operation of MPU during hard fault.

PRIVDEFENA

Bit 2: Enable priviliged software access to default memory map.

MPU_RNR

MPU region number register

Offset: 0x8, reset: 0X00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGION
rw
Toggle Fields.

REGION

Bits 0-7: MPU region.

MPU_RBAR

MPU region base address register

Offset: 0xC, reset: 0X00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw
VALID
rw
REGION
rw
Toggle Fields.

REGION

Bits 0-3: MPU region field.

VALID

Bit 4: MPU region number valid.

ADDR

Bits 5-31: Region base address field.

MPU_RASR

MPU region attribute and size register

Offset: 0x10, reset: 0X00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
XN
rw
AP
rw
TEX
rw
S
rw
C
rw
B
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRD
rw
SIZE
rw
ENABLE
rw
Toggle Fields.

ENABLE

Bit 0: Region enable bit..

SIZE

Bits 1-5: Size of the MPU protection region.

SRD

Bits 8-15: Subregion disable bits.

B

Bit 16: memory attribute.

C

Bit 17: memory attribute.

S

Bit 18: Shareable memory attribute.

TEX

Bits 19-21: memory attribute.

AP

Bits 24-26: Access permission.

XN

Bit 28: Instruction access disable bit.

NVIC

0xE000E100: Nested Vectored Interrupt Controller

3/99 fields covered. Toggle Registers.

ISER0

Interrupt Set-Enable Register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER1

Interrupt Set-Enable Register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER2

Interrupt Set-Enable Register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ICER0

Interrupt Clear-Enable Register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER1

Interrupt Clear-Enable Register

Offset: 0x84, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER2

Interrupt Clear-Enable Register

Offset: 0x88, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ISPR0

Interrupt Set-Pending Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR1

Interrupt Set-Pending Register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR2

Interrupt Set-Pending Register

Offset: 0x108, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ICPR0

Interrupt Clear-Pending Register

Offset: 0x180, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR1

Interrupt Clear-Pending Register

Offset: 0x184, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR2

Interrupt Clear-Pending Register

Offset: 0x188, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

IABR0

Interrupt Active Bit Register

Offset: 0x200, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle Fields.

ACTIVE

Bits 0-31: ACTIVE.

IABR1

Interrupt Active Bit Register

Offset: 0x204, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle Fields.

ACTIVE

Bits 0-31: ACTIVE.

IABR2

Interrupt Active Bit Register

Offset: 0x208, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle Fields.

ACTIVE

Bits 0-31: ACTIVE.

IPR0

Interrupt Priority Register

Offset: 0x300, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR1

Interrupt Priority Register

Offset: 0x304, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR2

Interrupt Priority Register

Offset: 0x308, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR3

Interrupt Priority Register

Offset: 0x30C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR4

Interrupt Priority Register

Offset: 0x310, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR5

Interrupt Priority Register

Offset: 0x314, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR6

Interrupt Priority Register

Offset: 0x318, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR7

Interrupt Priority Register

Offset: 0x31C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR8

Interrupt Priority Register

Offset: 0x320, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR9

Interrupt Priority Register

Offset: 0x324, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR10

Interrupt Priority Register

Offset: 0x328, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR11

Interrupt Priority Register

Offset: 0x32C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR12

Interrupt Priority Register

Offset: 0x330, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR13

Interrupt Priority Register

Offset: 0x334, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR14

Interrupt Priority Register

Offset: 0x338, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR15

Interrupt Priority Register

Offset: 0x33C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR16

Interrupt Priority Register

Offset: 0x340, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR17

Interrupt Priority Register

Offset: 0x344, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR18

Interrupt Priority Register

Offset: 0x348, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR19

Interrupt Priority Register

Offset: 0x34C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR20

Interrupt Priority Register

Offset: 0x350, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

NVIC_STIR

0xE000EF00: Nested vectored interrupt controller

0/1 fields covered. Toggle Registers.

STIR

Software trigger interrupt register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTID
rw
Toggle Fields.

INTID

Bits 0-8: Software generated interrupt ID.

OTG_FS_DEVICE

0x50000800: USB on the go full speed

38/204 fields covered. Toggle Registers.

FS_DCFG

OTG_FS device configuration register (OTG_FS_DCFG)

Offset: 0x0, reset: 0x02200000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PFIVL
rw
DAD
rw
NZLSOHSK
rw
DSPD
rw
Toggle Fields.

DSPD

Bits 0-1: Device speed.

NZLSOHSK

Bit 2: Non-zero-length status OUT handshake.

DAD

Bits 4-10: Device address.

PFIVL

Bits 11-12: Periodic frame interval.

FS_DCTL

OTG_FS device control register (OTG_FS_DCTL)

Offset: 0x4, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POPRGDNE
rw
CGONAK
rw
SGONAK
rw
CGINAK
rw
SGINAK
rw
TCTL
rw
GONSTS
r
GINSTS
r
SDIS
rw
RWUSIG
rw
Toggle Fields.

RWUSIG

Bit 0: Remote wakeup signaling.

SDIS

Bit 1: Soft disconnect.

GINSTS

Bit 2: Global IN NAK status.

GONSTS

Bit 3: Global OUT NAK status.

TCTL

Bits 4-6: Test control.

SGINAK

Bit 7: Set global IN NAK.

CGINAK

Bit 8: Clear global IN NAK.

SGONAK

Bit 9: Set global OUT NAK.

CGONAK

Bit 10: Clear global OUT NAK.

POPRGDNE

Bit 11: Power-on programming done.

FS_DSTS

OTG_FS device status register (OTG_FS_DSTS)

Offset: 0x8, reset: 0x00000010, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FNSOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNSOF
r
EERR
r
ENUMSPD
r
SUSPSTS
r
Toggle Fields.

SUSPSTS

Bit 0: Suspend status.

ENUMSPD

Bits 1-2: Enumerated speed.

EERR

Bit 3: Erratic error.

FNSOF

Bits 8-21: Frame number of the received SOF.

FS_DIEPMSK

OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)

Offset: 0x10, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPNEM
rw
INEPNMM
rw
ITTXFEMSK
rw
TOM
rw
EPDM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

TOM

Bit 3: Timeout condition mask (Non-isochronous endpoints).

ITTXFEMSK

Bit 4: IN token received when TxFIFO empty mask.

INEPNMM

Bit 5: IN token received with EP mismatch mask.

INEPNEM

Bit 6: IN endpoint NAK effective mask.

FS_DOEPMSK

OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)

Offset: 0x14, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTEPDM
rw
STUPM
rw
EPDM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

STUPM

Bit 3: SETUP phase done mask.

OTEPDM

Bit 4: OUT token received when endpoint disabled mask.

FS_DAINT

OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)

Offset: 0x18, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPINT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPINT
r
Toggle Fields.

IEPINT

Bits 0-15: IN endpoint interrupt bits.

OEPINT

Bits 16-31: OUT endpoint interrupt bits.

FS_DAINTMSK

OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPINT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPM
rw
Toggle Fields.

IEPM

Bits 0-15: IN EP interrupt mask bits.

OEPINT

Bits 16-31: OUT endpoint interrupt bits.

DVBUSDIS

OTG_FS device VBUS discharge time register

Offset: 0x28, reset: 0x000017D7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBUSDT
rw
Toggle Fields.

VBUSDT

Bits 0-15: Device VBUS discharge time.

DVBUSPULSE

OTG_FS device VBUS pulsing time register

Offset: 0x2C, reset: 0x000005B8, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DVBUSP
rw
Toggle Fields.

DVBUSP

Bits 0-11: Device VBUS pulsing time.

DIEPEMPMSK

OTG_FS device IN endpoint FIFO empty interrupt mask register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXFEM
rw
Toggle Fields.

INEPTXFEM

Bits 0-15: IN EP Tx FIFO empty interrupt mask bits.

FS_DIEPCTL0

OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)

Offset: 0x100, reset: 0x00000000, access: Unspecified

5/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
r
EPDIS
r
SNAK
w
CNAK
w
TXFNUM
rw
STALL
rw
EPTYP
r
NAKSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
r
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-1: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

DIEPINT0

device endpoint-x interrupt register

Offset: 0x108, reset: 0x00000080, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

DIEPTSIZ0

device endpoint-0 transfer size register

Offset: 0x110, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PKTCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-6: Transfer size.

PKTCNT

Bits 19-20: Packet count.

DTXFSTS0

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x118, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle Fields.

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

DIEPCTL1

OTG device endpoint-1 control register

Offset: 0x120, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM_SD1PID
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
Stall
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

Stall

Bit 21: Stall.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM_SD1PID

Bit 29: SODDFRM/SD1PID.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT1

device endpoint-1 interrupt register

Offset: 0x128, reset: 0x00000080, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

DIEPTSIZ1

device endpoint-1 transfer size register

Offset: 0x130, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DTXFSTS1

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x138, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle Fields.

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

DIEPCTL2

OTG device endpoint-2 control register

Offset: 0x140, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
Stall
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

Stall

Bit 21: Stall.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT2

device endpoint-2 interrupt register

Offset: 0x148, reset: 0x00000080, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

DIEPTSIZ2

device endpoint-2 transfer size register

Offset: 0x150, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DTXFSTS2

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x158, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle Fields.

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

DIEPCTL3

OTG device endpoint-3 control register

Offset: 0x160, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
Stall
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

Stall

Bit 21: Stall.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT3

device endpoint-3 interrupt register

Offset: 0x168, reset: 0x00000080, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

DIEPTSIZ3

device endpoint-3 transfer size register

Offset: 0x170, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DTXFSTS3

OTG_FS device IN endpoint transmit FIFO status register

Offset: 0x178, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle Fields.

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space available.

DOEPCTL0

device endpoint-0 control register

Offset: 0x300, reset: 0x00008000, access: Unspecified

5/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
w
EPDIS
r
SNAK
w
CNAK
w
Stall
rw
SNPM
rw
EPTYP
r
NAKSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
r
MPSIZ
r
Toggle Fields.

MPSIZ

Bits 0-1: MPSIZ.

USBAEP

Bit 15: USBAEP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

Stall

Bit 21: Stall.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT0

device endpoint-0 interrupt register

Offset: 0x308, reset: 0x00000080, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw
OTEPDIS
rw
STUP
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

DOEPTSIZ0

device OUT endpoint-0 transfer size register

Offset: 0x310, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STUPCNT
rw
PKTCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-6: Transfer size.

PKTCNT

Bit 19: Packet count.

STUPCNT

Bits 29-30: SETUP packet count.

DOEPCTL1

device endpoint-1 control register

Offset: 0x320, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
Stall
rw
SNPM
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

Stall

Bit 21: Stall.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT1

device endpoint-1 interrupt register

Offset: 0x328, reset: 0x00000080, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw
OTEPDIS
rw
STUP
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

DOEPTSIZ1

device OUT endpoint-1 transfer size register

Offset: 0x330, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

DOEPCTL2

device endpoint-2 control register

Offset: 0x340, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
Stall
rw
SNPM
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

Stall

Bit 21: Stall.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT2

device endpoint-2 interrupt register

Offset: 0x348, reset: 0x00000080, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw
OTEPDIS
rw
STUP
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

DOEPTSIZ2

device OUT endpoint-2 transfer size register

Offset: 0x350, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

DOEPCTL3

device endpoint-3 control register

Offset: 0x360, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
Stall
rw
SNPM
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPID

Bit 16: EONUM/DPID.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

Stall

Bit 21: Stall.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID/SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT3

device endpoint-3 interrupt register

Offset: 0x368, reset: 0x00000080, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2BSTUP
rw
OTEPDIS
rw
STUP
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

B2BSTUP

Bit 6: B2BSTUP.

DOEPTSIZ3

device OUT endpoint-3 transfer size register

Offset: 0x370, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

OTG_FS_GLOBAL

0x50000000: USB on the go full speed

32/115 fields covered. Toggle Registers.

FS_GOTGCTL

OTG_FS control and status register (OTG_FS_GOTGCTL)

Offset: 0x0, reset: 0x00000800, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSVLD
r
ASVLD
r
DBCT
r
CIDSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DHNPEN
rw
HSHNPEN
rw
HNPRQ
rw
HNGSCS
r
SRQ
rw
SRQSCS
r
Toggle Fields.

SRQSCS

Bit 0: Session request success.

SRQ

Bit 1: Session request.

HNGSCS

Bit 8: Host negotiation success.

HNPRQ

Bit 9: HNP request.

HSHNPEN

Bit 10: Host set HNP enable.

DHNPEN

Bit 11: Device HNP enabled.

CIDSTS

Bit 16: Connector ID status.

DBCT

Bit 17: Long/short debounce time.

ASVLD

Bit 18: A-session valid.

BSVLD

Bit 19: B-session valid.

FS_GOTGINT

OTG_FS interrupt register (OTG_FS_GOTGINT)

Offset: 0x4, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBCDNE
rw
ADTOCHG
rw
HNGDET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HNSSCHG
rw
SRSSCHG
rw
SEDET
rw
Toggle Fields.

SEDET

Bit 2: Session end detected.

SRSSCHG

Bit 8: Session request success status change.

HNSSCHG

Bit 9: Host negotiation success status change.

HNGDET

Bit 17: Host negotiation detected.

ADTOCHG

Bit 18: A-device timeout change.

DBCDNE

Bit 19: Debounce done.

FS_GAHBCFG

OTG_FS AHB configuration register (OTG_FS_GAHBCFG)

Offset: 0x8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFELVL
rw
TXFELVL
rw
GINT
rw
Toggle Fields.

GINT

Bit 0: Global interrupt mask.

TXFELVL

Bit 7: TxFIFO empty level.

PTXFELVL

Bit 8: Periodic TxFIFO empty level.

FS_GUSBCFG

OTG_FS USB configuration register (OTG_FS_GUSBCFG)

Offset: 0xC, reset: 0x00000A00, access: Unspecified

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTXPKT
rw
FDMOD
rw
FHMOD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRDT
rw
HNPCAP
rw
SRPCAP
rw
PHYSEL
w
TOCAL
rw
Toggle Fields.

TOCAL

Bits 0-2: FS timeout calibration.

PHYSEL

Bit 6: Full Speed serial transceiver select.

SRPCAP

Bit 8: SRP-capable.

HNPCAP

Bit 9: HNP-capable.

TRDT

Bits 10-13: USB turnaround time.

FHMOD

Bit 29: Force host mode.

FDMOD

Bit 30: Force device mode.

CTXPKT

Bit 31: Corrupt Tx packet.

FS_GRSTCTL

OTG_FS reset register (OTG_FS_GRSTCTL)

Offset: 0x10, reset: 0x20000000, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AHBIDL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFNUM
rw
TXFFLSH
rw
RXFFLSH
rw
FCRST
rw
HSRST
rw
CSRST
rw
Toggle Fields.

CSRST

Bit 0: Core soft reset.

HSRST

Bit 1: HCLK soft reset.

FCRST

Bit 2: Host frame counter reset.

RXFFLSH

Bit 4: RxFIFO flush.

TXFFLSH

Bit 5: TxFIFO flush.

TXFNUM

Bits 6-10: TxFIFO number.

AHBIDL

Bit 31: AHB master idle.

FS_GINTSTS

OTG_FS core interrupt register (OTG_FS_GINTSTS)

Offset: 0x14, reset: 0x04000020, access: Unspecified

11/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPINT
rw
SRQINT
rw
DISCINT
rw
CIDSCHG
rw
PTXFE
r
HCINT
r
HPRTINT
r
IPXFR_INCOMPISOOUT
rw
IISOIXFR
rw
OEPINT
r
IEPINT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPF
rw
ISOODRP
rw
ENUMDNE
rw
USBRST
rw
USBSUSP
rw
ESUSP
rw
GOUTNAKEFF
r
GINAKEFF
r
NPTXFE
r
RXFLVL
r
SOF
rw
OTGINT
r
MMIS
rw
CMOD
r
Toggle Fields.

CMOD

Bit 0: Current mode of operation.

MMIS

Bit 1: Mode mismatch interrupt.

OTGINT

Bit 2: OTG interrupt.

SOF

Bit 3: Start of frame.

RXFLVL

Bit 4: RxFIFO non-empty.

NPTXFE

Bit 5: Non-periodic TxFIFO empty.

GINAKEFF

Bit 6: Global IN non-periodic NAK effective.

GOUTNAKEFF

Bit 7: Global OUT NAK effective.

ESUSP

Bit 10: Early suspend.

USBSUSP

Bit 11: USB suspend.

USBRST

Bit 12: USB reset.

ENUMDNE

Bit 13: Enumeration done.

ISOODRP

Bit 14: Isochronous OUT packet dropped interrupt.

EOPF

Bit 15: End of periodic frame interrupt.

IEPINT

Bit 18: IN endpoint interrupt.

OEPINT

Bit 19: OUT endpoint interrupt.

IISOIXFR

Bit 20: Incomplete isochronous IN transfer.

IPXFR_INCOMPISOOUT

Bit 21: Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode).

HPRTINT

Bit 24: Host port interrupt.

HCINT

Bit 25: Host channels interrupt.

PTXFE

Bit 26: Periodic TxFIFO empty.

CIDSCHG

Bit 28: Connector ID status change.

DISCINT

Bit 29: Disconnect detected interrupt.

SRQINT

Bit 30: Session request/new session detected interrupt.

WKUPINT

Bit 31: Resume/remote wakeup detected interrupt.

FS_GINTMSK

OTG_FS interrupt mask register (OTG_FS_GINTMSK)

Offset: 0x18, reset: 0x00000000, access: Unspecified

1/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUIM
rw
SRQIM
rw
DISCINT
rw
CIDSCHGM
rw
PTXFEM
rw
HCIM
rw
PRTIM
r
IPXFRM_IISOOXFRM
rw
IISOIXFRM
rw
OEPINT
rw
IEPINT
rw
EPMISM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPFM
rw
ISOODRPM
rw
ENUMDNEM
rw
USBRST
rw
USBSUSPM
rw
ESUSPM
rw
GONAKEFFM
rw
GINAKEFFM
rw
NPTXFEM
rw
RXFLVLM
rw
SOFM
rw
OTGINT
rw
MMISM
rw
Toggle Fields.

MMISM

Bit 1: Mode mismatch interrupt mask.

OTGINT

Bit 2: OTG interrupt mask.

SOFM

Bit 3: Start of frame mask.

RXFLVLM

Bit 4: Receive FIFO non-empty mask.

NPTXFEM

Bit 5: Non-periodic TxFIFO empty mask.

GINAKEFFM

Bit 6: Global non-periodic IN NAK effective mask.

GONAKEFFM

Bit 7: Global OUT NAK effective mask.

ESUSPM

Bit 10: Early suspend mask.

USBSUSPM

Bit 11: USB suspend mask.

USBRST

Bit 12: USB reset mask.

ENUMDNEM

Bit 13: Enumeration done mask.

ISOODRPM

Bit 14: Isochronous OUT packet dropped interrupt mask.

EOPFM

Bit 15: End of periodic frame interrupt mask.

EPMISM

Bit 17: Endpoint mismatch interrupt mask.

IEPINT

Bit 18: IN endpoints interrupt mask.

OEPINT

Bit 19: OUT endpoints interrupt mask.

IISOIXFRM

Bit 20: Incomplete isochronous IN transfer mask.

IPXFRM_IISOOXFRM

Bit 21: Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode).

PRTIM

Bit 24: Host port interrupt mask.

HCIM

Bit 25: Host channels interrupt mask.

PTXFEM

Bit 26: Periodic TxFIFO empty mask.

CIDSCHGM

Bit 28: Connector ID status change mask.

DISCINT

Bit 29: Disconnect detected interrupt mask.

SRQIM

Bit 30: Session request/new session detected interrupt mask.

WUIM

Bit 31: Resume/remote wakeup detected interrupt mask.

FS_GRXSTSR_Host

OTG_FS Receive status debug read(Host mode)

Offset: 0x1C, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRMNUM
r
PKTSTS
r
DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r
BCNT
r
EPNUM
r
Toggle Fields.

EPNUM

Bits 0-3: Endpoint number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

FRMNUM

Bits 21-24: Frame number.

FS_GRXFSIZ

OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)

Offset: 0x24, reset: 0x00000200, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFD
rw
Toggle Fields.

RXFD

Bits 0-15: RxFIFO depth.

FS_GNPTXFSIZ_Host

OTG_FS non-periodic transmit FIFO size register (Host mode)

Offset: 0x28, reset: 0x00000200, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFSA
rw
Toggle Fields.

NPTXFSA

Bits 0-15: Non-periodic transmit RAM start address.

NPTXFD

Bits 16-31: Non-periodic TxFIFO depth.

FS_GNPTXSTS

OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)

Offset: 0x2C, reset: 0x00080200, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXQTOP
r
NPTQXSAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFSAV
r
Toggle Fields.

NPTXFSAV

Bits 0-15: Non-periodic TxFIFO space available.

NPTQXSAV

Bits 16-23: Non-periodic transmit request queue space available.

NPTXQTOP

Bits 24-30: Top of the non-periodic transmit request queue.

FS_GCCFG

OTG_FS general core configuration register (OTG_FS_GCCFG)

Offset: 0x38, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SOFOUTEN
rw
VBUSBSEN
rw
VBUSASEN
rw
PWRDWN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PWRDWN

Bit 16: Power down.

VBUSASEN

Bit 18: Enable the VBUS sensing device.

VBUSBSEN

Bit 19: Enable the VBUS sensing device.

SOFOUTEN

Bit 20: SOF output enable.

FS_CID

core ID register

Offset: 0x3C, reset: 0x00001000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRODUCT_ID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRODUCT_ID
rw
Toggle Fields.

PRODUCT_ID

Bits 0-31: Product ID field.

FS_HPTXFSIZ

OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)

Offset: 0x100, reset: 0x02000600, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXFSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXSA
rw
Toggle Fields.

PTXSA

Bits 0-15: Host periodic TxFIFO start address.

PTXFSIZ

Bits 16-31: Host periodic TxFIFO depth.

FS_DIEPTXF1

OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)

Offset: 0x104, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle Fields.

INEPTXSA

Bits 0-15: IN endpoint FIFO2 transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

FS_DIEPTXF2

OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)

Offset: 0x108, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle Fields.

INEPTXSA

Bits 0-15: IN endpoint FIFO3 transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

FS_DIEPTXF3

OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)

Offset: 0x10C, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle Fields.

INEPTXSA

Bits 0-15: IN endpoint FIFO4 transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_FS_HOST

0x50000400: USB on the go full speed

10/279 fields covered. Toggle Registers.

FS_HCFG

OTG_FS host configuration register (OTG_FS_HCFG)

Offset: 0x0, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSLSS
r
FSLSPCS
rw
Toggle Fields.

FSLSPCS

Bits 0-1: FS/LS PHY clock select.

FSLSS

Bit 2: FS- and LS-only support.

HFIR

OTG_FS Host frame interval register

Offset: 0x4, reset: 0x0000EA60, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRIVL
rw
Toggle Fields.

FRIVL

Bits 0-15: Frame interval.

FS_HFNUM

OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)

Offset: 0x8, reset: 0x00003FFF, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTREM
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRNUM
r
Toggle Fields.

FRNUM

Bits 0-15: Frame number.

FTREM

Bits 16-31: Frame time remaining.

FS_HPTXSTS

OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)

Offset: 0x10, reset: 0x00080100, access: Unspecified

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXQTOP
r
PTXQSAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFSAVL
rw
Toggle Fields.

PTXFSAVL

Bits 0-15: Periodic transmit data FIFO space available.

PTXQSAV

Bits 16-23: Periodic transmit request queue space available.

PTXQTOP

Bits 24-31: Top of the periodic transmit request queue.

HAINT

OTG_FS Host all channels interrupt register

Offset: 0x14, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HAINT
r
Toggle Fields.

HAINT

Bits 0-15: Channel interrupts.

HAINTMSK

OTG_FS host all channels interrupt mask register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HAINTM
rw
Toggle Fields.

HAINTM

Bits 0-15: Channel interrupt mask.

FS_HPRT

OTG_FS host port control and status register (OTG_FS_HPRT)

Offset: 0x40, reset: 0x00000000, access: Unspecified

4/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PSPD
r
PTCTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTCTL
rw
PPWR
rw
PLSTS
r
PRST
rw
PSUSP
rw
PRES
rw
POCCHNG
rw
POCA
r
PENCHNG
rw
PENA
rw
PCDET
rw
PCSTS
r
Toggle Fields.

PCSTS

Bit 0: Port connect status.

PCDET

Bit 1: Port connect detected.

PENA

Bit 2: Port enable.

PENCHNG

Bit 3: Port enable/disable change.

POCA

Bit 4: Port overcurrent active.

POCCHNG

Bit 5: Port overcurrent change.

PRES

Bit 6: Port resume.

PSUSP

Bit 7: Port suspend.

PRST

Bit 8: Port reset.

PLSTS

Bits 10-11: Port line status.

PPWR

Bit 12: Port power.

PTCTL

Bits 13-16: Port test control.

PSPD

Bits 17-18: Port speed.

FS_HCCHAR0

OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)

Offset: 0x100, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MCNT
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT0

OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)

Offset: 0x108, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
ACK
rw
NAK
rw
STALL
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK0

OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)

Offset: 0x10C, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ0

OTG_FS host channel-0 transfer size register

Offset: 0x110, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR1

OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)

Offset: 0x120, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MCNT
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT1

OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)

Offset: 0x128, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
ACK
rw
NAK
rw
STALL
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK1

OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)

Offset: 0x12C, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ1

OTG_FS host channel-1 transfer size register

Offset: 0x130, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR2

OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)

Offset: 0x140, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MCNT
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT2

OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)

Offset: 0x148, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
ACK
rw
NAK
rw
STALL
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK2

OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)

Offset: 0x14C, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ2

OTG_FS host channel-2 transfer size register

Offset: 0x150, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR3

OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)

Offset: 0x160, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MCNT
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT3

OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)

Offset: 0x168, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
ACK
rw
NAK
rw
STALL
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK3

OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)

Offset: 0x16C, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ3

OTG_FS host channel-3 transfer size register

Offset: 0x170, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR4

OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)

Offset: 0x180, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MCNT
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT4

OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)

Offset: 0x188, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
ACK
rw
NAK
rw
STALL
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK4

OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)

Offset: 0x18C, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ4

OTG_FS host channel-x transfer size register

Offset: 0x190, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR5

OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)

Offset: 0x1A0, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MCNT
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT5

OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)

Offset: 0x1A8, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
ACK
rw
NAK
rw
STALL
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK5

OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)

Offset: 0x1AC, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ5

OTG_FS host channel-5 transfer size register

Offset: 0x1B0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR6

OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)

Offset: 0x1C0, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MCNT
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT6

OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)

Offset: 0x1C8, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
ACK
rw
NAK
rw
STALL
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK6

OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)

Offset: 0x1CC, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ6

OTG_FS host channel-6 transfer size register

Offset: 0x1D0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_HCCHAR7

OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)

Offset: 0x1E0, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MCNT
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MCNT

Bits 20-21: Multicount.

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

FS_HCINT7

OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)

Offset: 0x1E8, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
ACK
rw
NAK
rw
STALL
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

FS_HCINTMSK7

OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)

Offset: 0x1EC, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

FS_HCTSIZ7

OTG_FS host channel-7 transfer size register

Offset: 0x1F0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_FS_PWRCLK

0x50000E00: USB on the go full speed

0/3 fields covered. Toggle Registers.

FS_PCGCCTL

OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)

Offset: 0x0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYSUSP
rw
GATEHCLK
rw
STPPCLK
rw
Toggle Fields.

STPPCLK

Bit 0: Stop PHY clock.

GATEHCLK

Bit 1: Gate HCLK.

PHYSUSP

Bit 4: PHY Suspended.

OTG_HS_DEVICE

0x40040800: USB on the go high speed

49/403 fields covered. Toggle Registers.

OTG_HS_DCFG

OTG_HS device configuration register

Offset: 0x0, reset: 0x02200000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERSCHIVL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PFIVL
rw
DAD
rw
NZLSOHSK
rw
DSPD
rw
Toggle Fields.

DSPD

Bits 0-1: Device speed.

NZLSOHSK

Bit 2: Nonzero-length status OUT handshake.

DAD

Bits 4-10: Device address.

PFIVL

Bits 11-12: Periodic (micro)frame interval.

PERSCHIVL

Bits 24-25: Periodic scheduling interval.

OTG_HS_DCTL

OTG_HS device control register

Offset: 0x4, reset: 0x0, access: Unspecified

2/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POPRGDNE
rw
CGONAK
w
SGONAK
w
CGINAK
w
SGINAK
w
TCTL
rw
GONSTS
r
GINSTS
r
SDIS
rw
RWUSIG
rw
Toggle Fields.

RWUSIG

Bit 0: Remote wakeup signaling.

SDIS

Bit 1: Soft disconnect.

GINSTS

Bit 2: Global IN NAK status.

GONSTS

Bit 3: Global OUT NAK status.

TCTL

Bits 4-6: Test control.

SGINAK

Bit 7: Set global IN NAK.

CGINAK

Bit 8: Clear global IN NAK.

SGONAK

Bit 9: Set global OUT NAK.

CGONAK

Bit 10: Clear global OUT NAK.

POPRGDNE

Bit 11: Power-on programming done.

OTG_HS_DSTS

OTG_HS device status register

Offset: 0x8, reset: 0x00000010, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FNSOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNSOF
r
EERR
r
ENUMSPD
r
SUSPSTS
r
Toggle Fields.

SUSPSTS

Bit 0: Suspend status.

ENUMSPD

Bits 1-2: Enumerated speed.

EERR

Bit 3: Erratic error.

FNSOF

Bits 8-21: Frame number of the received SOF.

OTG_HS_DIEPMSK

OTG_HS device IN endpoint common interrupt mask register

Offset: 0x10, reset: 0x0, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIM
rw
TXFURM
rw
INEPNEM
rw
INEPNMM
rw
ITTXFEMSK
rw
TOM
rw
EPDM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

TOM

Bit 3: Timeout condition mask (nonisochronous endpoints).

ITTXFEMSK

Bit 4: IN token received when TxFIFO empty mask.

INEPNMM

Bit 5: IN token received with EP mismatch mask.

INEPNEM

Bit 6: IN endpoint NAK effective mask.

TXFURM

Bit 8: FIFO underrun mask.

BIM

Bit 9: BNA interrupt mask.

OTG_HS_DOEPMSK

OTG_HS device OUT endpoint common interrupt mask register

Offset: 0x14, reset: 0x0, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOIM
rw
OPEM
rw
B2BSTUP
rw
OTEPDM
rw
STUPM
rw
EPDM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

STUPM

Bit 3: SETUP phase done mask.

OTEPDM

Bit 4: OUT token received when endpoint disabled mask.

B2BSTUP

Bit 6: Back-to-back SETUP packets received mask.

OPEM

Bit 8: OUT packet error mask.

BOIM

Bit 9: BNA interrupt mask.

OTG_HS_DAINT

OTG_HS device all endpoints interrupt register

Offset: 0x18, reset: 0x0, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPINT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPINT
r
Toggle Fields.

IEPINT

Bits 0-15: IN endpoint interrupt bits.

OEPINT

Bits 16-31: OUT endpoint interrupt bits.

OTG_HS_DAINTMSK

OTG_HS all endpoints interrupt mask register

Offset: 0x1C, reset: 0x0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPM
rw
Toggle Fields.

IEPM

Bits 0-15: IN EP interrupt mask bits.

OEPM

Bits 16-31: OUT EP interrupt mask bits.

OTG_HS_DVBUSDIS

OTG_HS device VBUS discharge time register

Offset: 0x28, reset: 0x000017D7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBUSDT
rw
Toggle Fields.

VBUSDT

Bits 0-15: Device VBUS discharge time.

OTG_HS_DVBUSPULSE

OTG_HS device VBUS pulsing time register

Offset: 0x2C, reset: 0x000005B8, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DVBUSP
rw
Toggle Fields.

DVBUSP

Bits 0-11: Device VBUS pulsing time.

OTG_HS_DTHRCTL

OTG_HS Device threshold control register

Offset: 0x30, reset: 0x0, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARPEN
rw
RXTHRLEN
rw
RXTHREN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTHRLEN
rw
ISOTHREN
rw
NONISOTHREN
rw
Toggle Fields.

NONISOTHREN

Bit 0: Nonisochronous IN endpoints threshold enable.

ISOTHREN

Bit 1: ISO IN endpoint threshold enable.

TXTHRLEN

Bits 2-10: Transmit threshold length.

RXTHREN

Bit 16: Receive threshold enable.

RXTHRLEN

Bits 17-25: Receive threshold length.

ARPEN

Bit 27: Arbiter parking enable.

OTG_HS_DIEPEMPMSK

OTG_HS device IN endpoint FIFO empty interrupt mask register

Offset: 0x34, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXFEM
rw
Toggle Fields.

INEPTXFEM

Bits 0-15: IN EP Tx FIFO empty interrupt mask bits.

OTG_HS_DEACHINT

OTG_HS device each endpoint interrupt register

Offset: 0x38, reset: 0x0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEP1INT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEP1INT
rw
Toggle Fields.

IEP1INT

Bit 1: IN endpoint 1interrupt bit.

OEP1INT

Bit 17: OUT endpoint 1 interrupt bit.

OTG_HS_DEACHINTMSK

OTG_HS device each endpoint interrupt register mask

Offset: 0x3C, reset: 0x0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEP1INTM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEP1INTM
rw
Toggle Fields.

IEP1INTM

Bit 1: IN Endpoint 1 interrupt mask bit.

OEP1INTM

Bit 17: OUT Endpoint 1 interrupt mask bit.

OTG_HS_DIEPEACHMSK1

OTG_HS device each in endpoint-1 interrupt register

Offset: 0x40, reset: 0x0, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAKM
rw
BIM
rw
TXFURM
rw
INEPNEM
rw
INEPNMM
rw
ITTXFEMSK
rw
TOM
rw
EPDM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

TOM

Bit 3: Timeout condition mask (nonisochronous endpoints).

ITTXFEMSK

Bit 4: IN token received when TxFIFO empty mask.

INEPNMM

Bit 5: IN token received with EP mismatch mask.

INEPNEM

Bit 6: IN endpoint NAK effective mask.

TXFURM

Bit 8: FIFO underrun mask.

BIM

Bit 9: BNA interrupt mask.

NAKM

Bit 13: NAK interrupt mask.

OTG_HS_DOEPEACHMSK1

OTG_HS device each OUT endpoint-1 interrupt register

Offset: 0x80, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYETM
rw
NAKM
rw
BERRM
rw
BIM
rw
TXFURM
rw
INEPNEM
rw
INEPNMM
rw
ITTXFEMSK
rw
TOM
rw
EPDM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed interrupt mask.

EPDM

Bit 1: Endpoint disabled interrupt mask.

TOM

Bit 3: Timeout condition mask.

ITTXFEMSK

Bit 4: IN token received when TxFIFO empty mask.

INEPNMM

Bit 5: IN token received with EP mismatch mask.

INEPNEM

Bit 6: IN endpoint NAK effective mask.

TXFURM

Bit 8: OUT packet error mask.

BIM

Bit 9: BNA interrupt mask.

BERRM

Bit 12: Bubble error interrupt mask.

NAKM

Bit 13: NAK interrupt mask.

NYETM

Bit 14: NYET interrupt mask.

OTG_HS_DIEPCTL0

OTG device endpoint-0 control register

Offset: 0x100, reset: 0x0, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
Stall
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

Stall

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DIEPINT0

OTG device endpoint-0 interrupt register

Offset: 0x108, reset: 0x00000080, access: Unspecified

1/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

OTG_HS_DIEPTSIZ0

OTG_HS device IN endpoint 0 transfer size register

Offset: 0x110, reset: 0x0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PKTCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-6: Transfer size.

PKTCNT

Bits 19-20: Packet count.

OTG_HS_DIEPDMA1

OTG_HS device endpoint-1 DMA address register

Offset: 0x114, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

OTG_HS_DTXFSTS0

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x118, reset: 0x0, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle Fields.

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

OTG_HS_DIEPCTL1

OTG device endpoint-1 control register

Offset: 0x120, reset: 0x0, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
Stall
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

Stall

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DIEPINT1

OTG device endpoint-1 interrupt register

Offset: 0x128, reset: 0x0, access: Unspecified

1/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

OTG_HS_DIEPTSIZ1

OTG_HS device endpoint transfer size register

Offset: 0x130, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

OTG_HS_DIEPDMA2

OTG_HS device endpoint-2 DMA address register

Offset: 0x134, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

OTG_HS_DTXFSTS1

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x138, reset: 0x0, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle Fields.

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

OTG_HS_DIEPCTL2

OTG device endpoint-2 control register

Offset: 0x140, reset: 0x0, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
Stall
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

Stall

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DIEPINT2

OTG device endpoint-2 interrupt register

Offset: 0x148, reset: 0x0, access: Unspecified

1/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

OTG_HS_DIEPTSIZ2

OTG_HS device endpoint transfer size register

Offset: 0x150, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

OTG_HS_DIEPDMA3

OTG_HS device endpoint-3 DMA address register

Offset: 0x154, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

OTG_HS_DTXFSTS2

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x158, reset: 0x0, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle Fields.

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

OTG_HS_DIEPCTL3

OTG device endpoint-3 control register

Offset: 0x160, reset: 0x0, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
Stall
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

Stall

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DIEPINT3

OTG device endpoint-3 interrupt register

Offset: 0x168, reset: 0x0, access: Unspecified

1/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

OTG_HS_DIEPTSIZ3

OTG_HS device endpoint transfer size register

Offset: 0x170, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

OTG_HS_DIEPDMA4

OTG_HS device endpoint-4 DMA address register

Offset: 0x174, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

OTG_HS_DTXFSTS3

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x178, reset: 0x0, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle Fields.

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

OTG_HS_DIEPCTL4

OTG device endpoint-4 control register

Offset: 0x180, reset: 0x0, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
Stall
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

Stall

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DIEPINT4

OTG device endpoint-4 interrupt register

Offset: 0x188, reset: 0x0, access: Unspecified

1/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

OTG_HS_DIEPTSIZ4

OTG_HS device endpoint transfer size register

Offset: 0x190, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

OTG_HS_DIEPDMA5

OTG_HS device endpoint-5 DMA address register

Offset: 0x194, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

OTG_HS_DTXFSTS4

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x198, reset: 0x0, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle Fields.

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

OTG_HS_DIEPCTL5

OTG device endpoint-5 control register

Offset: 0x1A0, reset: 0x0, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
Stall
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

Stall

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DIEPINT5

OTG device endpoint-5 interrupt register

Offset: 0x1A8, reset: 0x0, access: Unspecified

1/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

OTG_HS_DIEPTSIZ5

OTG_HS device endpoint transfer size register

Offset: 0x1B0, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

OTG_HS_DTXFSTS5

OTG_HS device IN endpoint transmit FIFO status register

Offset: 0x1B8, reset: 0x0, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle Fields.

INEPTFSAV

Bits 0-15: IN endpoint TxFIFO space avail.

OTG_HS_DIEPCTL6

OTG device endpoint-6 control register

Offset: 0x1C0, reset: 0x0, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
Stall
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

Stall

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DIEPINT6

OTG device endpoint-6 interrupt register

Offset: 0x1C8, reset: 0x0, access: Unspecified

1/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

OTG_HS_DIEPCTL7

OTG device endpoint-7 control register

Offset: 0x1E0, reset: 0x0, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
TXFNUM
rw
Stall
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even/odd frame.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

Stall

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DIEPINT7

OTG device endpoint-7 interrupt register

Offset: 0x1E8, reset: 0x0, access: Unspecified

1/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw
BERR
rw
PKTDRPSTS
rw
BNA
rw
TXFIFOUDRN
rw
TXFE
r
INEPNE
rw
ITTXFE
rw
TOC
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

TOC

Bit 3: Timeout condition.

ITTXFE

Bit 4: IN token received when TxFIFO is empty.

INEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

TXFIFOUDRN

Bit 8: Transmit Fifo Underrun.

BNA

Bit 9: Buffer not available interrupt.

PKTDRPSTS

Bit 11: Packet dropped status.

BERR

Bit 12: Babble error interrupt.

NAK

Bit 13: NAK interrupt.

OTG_HS_DOEPCTL0

OTG_HS device control OUT endpoint 0 control register

Offset: 0x300, reset: 0x00008000, access: Unspecified

5/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
w
EPDIS
r
SNAK
w
CNAK
w
Stall
rw
SNPM
rw
EPTYP
r
NAKSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
r
MPSIZ
r
Toggle Fields.

MPSIZ

Bits 0-1: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

SNPM

Bit 20: Snoop mode.

Stall

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DOEPINT0

OTG_HS device endpoint-0 interrupt register

Offset: 0x308, reset: 0x00000080, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw
B2BSTUP
rw
OTEPDIS
rw
STUP
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

STUP

Bit 3: SETUP phase done.

OTEPDIS

Bit 4: OUT token received when endpoint disabled.

B2BSTUP

Bit 6: Back-to-back SETUP packets received.

NYET

Bit 14: NYET interrupt.

OTG_HS_DOEPTSIZ0

OTG_HS device endpoint-1 transfer size register

Offset: 0x310, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STUPCNT
rw
PKTCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-6: Transfer size.

PKTCNT

Bit 19: Packet count.

STUPCNT

Bits 29-30: SETUP packet count.

OTG_HS_DOEPCTL1

OTG device endpoint-1 control register

Offset: 0x320, reset: 0x0, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
Stall
rw
SNPM
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even odd frame/Endpoint data PID.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

SNPM

Bit 20: Snoop mode.

Stall

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID/Set even frame.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DOEPINT1

OTG_HS device endpoint-1 interrupt register

Offset: 0x328, reset: 0x0, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw
B2BSTUP
rw
OTEPDIS
rw
STUP
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

STUP

Bit 3: SETUP phase done.

OTEPDIS

Bit 4: OUT token received when endpoint disabled.

B2BSTUP

Bit 6: Back-to-back SETUP packets received.

NYET

Bit 14: NYET interrupt.

OTG_HS_DOEPTSIZ1

OTG_HS device endpoint-2 transfer size register

Offset: 0x330, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

OTG_HS_DOEPCTL2

OTG device endpoint-2 control register

Offset: 0x340, reset: 0x0, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
Stall
rw
SNPM
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even odd frame/Endpoint data PID.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

SNPM

Bit 20: Snoop mode.

Stall

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID/Set even frame.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DOEPINT2

OTG_HS device endpoint-2 interrupt register

Offset: 0x348, reset: 0x0, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw
B2BSTUP
rw
OTEPDIS
rw
STUP
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

STUP

Bit 3: SETUP phase done.

OTEPDIS

Bit 4: OUT token received when endpoint disabled.

B2BSTUP

Bit 6: Back-to-back SETUP packets received.

NYET

Bit 14: NYET interrupt.

OTG_HS_DOEPTSIZ2

OTG_HS device endpoint-3 transfer size register

Offset: 0x350, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

OTG_HS_DOEPCTL3

OTG device endpoint-3 control register

Offset: 0x360, reset: 0x0, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw
EPDIS
rw
SODDFRM
w
SD0PID_SEVNFRM
w
SNAK
w
CNAK
w
Stall
rw
SNPM
rw
EPTYP
rw
NAKSTS
r
EONUM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

USBAEP

Bit 15: USB active endpoint.

EONUM_DPID

Bit 16: Even odd frame/Endpoint data PID.

NAKSTS

Bit 17: NAK status.

EPTYP

Bits 18-19: Endpoint type.

SNPM

Bit 20: Snoop mode.

Stall

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVNFRM

Bit 28: Set DATA0 PID/Set even frame.

SODDFRM

Bit 29: Set odd frame.

EPDIS

Bit 30: Endpoint disable.

EPENA

Bit 31: Endpoint enable.

OTG_HS_DOEPINT3

OTG_HS device endpoint-3 interrupt register

Offset: 0x368, reset: 0x0, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw
B2BSTUP
rw
OTEPDIS
rw
STUP
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

STUP

Bit 3: SETUP phase done.

OTEPDIS

Bit 4: OUT token received when endpoint disabled.

B2BSTUP

Bit 6: Back-to-back SETUP packets received.

NYET

Bit 14: NYET interrupt.

OTG_HS_DOEPTSIZ3

OTG_HS device endpoint-4 transfer size register

Offset: 0x370, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

OTG_HS_DOEPINT4

OTG_HS device endpoint-4 interrupt register

Offset: 0x388, reset: 0x0, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw
B2BSTUP
rw
OTEPDIS
rw
STUP
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

STUP

Bit 3: SETUP phase done.

OTEPDIS

Bit 4: OUT token received when endpoint disabled.

B2BSTUP

Bit 6: Back-to-back SETUP packets received.

NYET

Bit 14: NYET interrupt.

OTG_HS_DOEPTSIZ4

OTG_HS device endpoint-5 transfer size register

Offset: 0x390, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

RXDPID_STUPCNT

Bits 29-30: Received data PID/SETUP packet count.

OTG_HS_DOEPINT5

OTG_HS device endpoint-5 interrupt register

Offset: 0x3A8, reset: 0x0, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw
B2BSTUP
rw
OTEPDIS
rw
STUP
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

STUP

Bit 3: SETUP phase done.

OTEPDIS

Bit 4: OUT token received when endpoint disabled.

B2BSTUP

Bit 6: Back-to-back SETUP packets received.

NYET

Bit 14: NYET interrupt.

OTG_HS_DOEPINT6

OTG_HS device endpoint-6 interrupt register

Offset: 0x3C8, reset: 0x0, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw
B2BSTUP
rw
OTEPDIS
rw
STUP
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

STUP

Bit 3: SETUP phase done.

OTEPDIS

Bit 4: OUT token received when endpoint disabled.

B2BSTUP

Bit 6: Back-to-back SETUP packets received.

NYET

Bit 14: NYET interrupt.

OTG_HS_DOEPINT7

OTG_HS device endpoint-7 interrupt register

Offset: 0x3E8, reset: 0x0, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw
B2BSTUP
rw
OTEPDIS
rw
STUP
rw
EPDISD
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed interrupt.

EPDISD

Bit 1: Endpoint disabled interrupt.

STUP

Bit 3: SETUP phase done.

OTEPDIS

Bit 4: OUT token received when endpoint disabled.

B2BSTUP

Bit 6: Back-to-back SETUP packets received.

NYET

Bit 14: NYET interrupt.

OTG_HS_GLOBAL

0x40040000: USB on the go high speed

41/148 fields covered. Toggle Registers.

OTG_HS_GOTGCTL

OTG_HS control and status register

Offset: 0x0, reset: 0x00000800, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSVLD
r
ASVLD
r
DBCT
r
CIDSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DHNPEN
rw
HSHNPEN
rw
HNPRQ
rw
HNGSCS
r
SRQ
rw
SRQSCS
r
Toggle Fields.

SRQSCS

Bit 0: Session request success.

SRQ

Bit 1: Session request.

HNGSCS

Bit 8: Host negotiation success.

HNPRQ

Bit 9: HNP request.

HSHNPEN

Bit 10: Host set HNP enable.

DHNPEN

Bit 11: Device HNP enabled.

CIDSTS

Bit 16: Connector ID status.

DBCT

Bit 17: Long/short debounce time.

ASVLD

Bit 18: A-session valid.

BSVLD

Bit 19: B-session valid.

OTG_HS_GOTGINT

OTG_HS interrupt register

Offset: 0x4, reset: 0x0, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBCDNE
rw
ADTOCHG
rw
HNGDET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HNSSCHG
rw
SRSSCHG
rw
SEDET
rw
Toggle Fields.

SEDET

Bit 2: Session end detected.

SRSSCHG

Bit 8: Session request success status change.

HNSSCHG

Bit 9: Host negotiation success status change.

HNGDET

Bit 17: Host negotiation detected.

ADTOCHG

Bit 18: A-device timeout change.

DBCDNE

Bit 19: Debounce done.

OTG_HS_GAHBCFG

OTG_HS AHB configuration register

Offset: 0x8, reset: 0x0, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFELVL
rw
TXFELVL
rw
DMAEN
rw
HBSTLEN
rw
GINT
rw
Toggle Fields.

GINT

Bit 0: Global interrupt mask.

HBSTLEN

Bits 1-4: Burst length/type.

DMAEN

Bit 5: DMA enable.

TXFELVL

Bit 7: TxFIFO empty level.

PTXFELVL

Bit 8: Periodic TxFIFO empty level.

OTG_HS_GUSBCFG

OTG_HS USB configuration register

Offset: 0xC, reset: 0x00000A00, access: Unspecified

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTXPKT
rw
FDMOD
rw
FHMOD
rw
ULPIIPD
rw
PTCI
rw
PCCI
rw
TSDPS
rw
ULPIEVBUSI
rw
ULPIEVBUSD
rw
ULPICSM
rw
ULPIAR
rw
ULPIFSLS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYLPCS
rw
TRDT
rw
HNPCAP
rw
SRPCAP
rw
PHYSEL
w
TOCAL
rw
Toggle Fields.

TOCAL

Bits 0-2: FS timeout calibration.

PHYSEL

Bit 6: USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select.

SRPCAP

Bit 8: SRP-capable.

HNPCAP

Bit 9: HNP-capable.

TRDT

Bits 10-13: USB turnaround time.

PHYLPCS

Bit 15: PHY Low-power clock select.

ULPIFSLS

Bit 17: ULPI FS/LS select.

ULPIAR

Bit 18: ULPI Auto-resume.

ULPICSM

Bit 19: ULPI Clock SuspendM.

ULPIEVBUSD

Bit 20: ULPI External VBUS Drive.

ULPIEVBUSI

Bit 21: ULPI external VBUS indicator.

TSDPS

Bit 22: TermSel DLine pulsing selection.

PCCI

Bit 23: Indicator complement.

PTCI

Bit 24: Indicator pass through.

ULPIIPD

Bit 25: ULPI interface protect disable.

FHMOD

Bit 29: Forced host mode.

FDMOD

Bit 30: Forced peripheral mode.

CTXPKT

Bit 31: Corrupt Tx packet.

OTG_HS_GRSTCTL

OTG_HS reset register

Offset: 0x10, reset: 0x20000000, access: Unspecified

2/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AHBIDL
r
DMAREQ
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFNUM
rw
TXFFLSH
rw
RXFFLSH
rw
FCRST
rw
HSRST
rw
CSRST
rw
Toggle Fields.

CSRST

Bit 0: Core soft reset.

HSRST

Bit 1: HCLK soft reset.

FCRST

Bit 2: Host frame counter reset.

RXFFLSH

Bit 4: RxFIFO flush.

TXFFLSH

Bit 5: TxFIFO flush.

TXFNUM

Bits 6-10: TxFIFO number.

DMAREQ

Bit 30: DMA request signal.

AHBIDL

Bit 31: AHB master idle.

OTG_HS_GINTSTS

OTG_HS core interrupt register

Offset: 0x14, reset: 0x04000020, access: Unspecified

11/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUINT
rw
SRQINT
rw
DISCINT
rw
CIDSCHG
rw
PTXFE
r
HCINT
r
HPRTINT
r
DATAFSUSP
rw
PXFR_INCOMPISOOUT
rw
IISOIXFR
rw
OEPINT
r
IEPINT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPF
rw
ISOODRP
rw
ENUMDNE
rw
USBRST
rw
USBSUSP
rw
ESUSP
rw
BOUTNAKEFF
r
GINAKEFF
r
NPTXFE
r
RXFLVL
r
SOF
rw
OTGINT
r
MMIS
rw
CMOD
r
Toggle Fields.

CMOD

Bit 0: Current mode of operation.

MMIS

Bit 1: Mode mismatch interrupt.

OTGINT

Bit 2: OTG interrupt.

SOF

Bit 3: Start of frame.

RXFLVL

Bit 4: RxFIFO nonempty.

NPTXFE

Bit 5: Nonperiodic TxFIFO empty.

GINAKEFF

Bit 6: Global IN nonperiodic NAK effective.

BOUTNAKEFF

Bit 7: Global OUT NAK effective.

ESUSP

Bit 10: Early suspend.

USBSUSP

Bit 11: USB suspend.

USBRST

Bit 12: USB reset.

ENUMDNE

Bit 13: Enumeration done.

ISOODRP

Bit 14: Isochronous OUT packet dropped interrupt.

EOPF

Bit 15: End of periodic frame interrupt.

IEPINT

Bit 18: IN endpoint interrupt.

OEPINT

Bit 19: OUT endpoint interrupt.

IISOIXFR

Bit 20: Incomplete isochronous IN transfer.

PXFR_INCOMPISOOUT

Bit 21: Incomplete periodic transfer.

DATAFSUSP

Bit 22: Data fetch suspended.

HPRTINT

Bit 24: Host port interrupt.

HCINT

Bit 25: Host channels interrupt.

PTXFE

Bit 26: Periodic TxFIFO empty.

CIDSCHG

Bit 28: Connector ID status change.

DISCINT

Bit 29: Disconnect detected interrupt.

SRQINT

Bit 30: Session request/new session detected interrupt.

WKUINT

Bit 31: Resume/remote wakeup detected interrupt.

OTG_HS_GINTMSK

OTG_HS interrupt mask register

Offset: 0x18, reset: 0x0, access: Unspecified

1/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUIM
rw
SRQIM
rw
DISCINT
rw
CIDSCHGM
rw
PTXFEM
rw
HCIM
rw
PRTIM
r
FSUSPM
rw
PXFRM_IISOOXFRM
rw
IISOIXFRM
rw
OEPINT
rw
IEPINT
rw
EPMISM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPFM
rw
ISOODRPM
rw
ENUMDNEM
rw
USBRST
rw
USBSUSPM
rw
ESUSPM
rw
GONAKEFFM
rw
GINAKEFFM
rw
NPTXFEM
rw
RXFLVLM
rw
SOFM
rw
OTGINT
rw
MMISM
rw
Toggle Fields.

MMISM

Bit 1: Mode mismatch interrupt mask.

OTGINT

Bit 2: OTG interrupt mask.

SOFM

Bit 3: Start of frame mask.

RXFLVLM

Bit 4: Receive FIFO nonempty mask.

NPTXFEM

Bit 5: Nonperiodic TxFIFO empty mask.

GINAKEFFM

Bit 6: Global nonperiodic IN NAK effective mask.

GONAKEFFM

Bit 7: Global OUT NAK effective mask.

ESUSPM

Bit 10: Early suspend mask.

USBSUSPM

Bit 11: USB suspend mask.

USBRST

Bit 12: USB reset mask.

ENUMDNEM

Bit 13: Enumeration done mask.

ISOODRPM

Bit 14: Isochronous OUT packet dropped interrupt mask.

EOPFM

Bit 15: End of periodic frame interrupt mask.

EPMISM

Bit 17: Endpoint mismatch interrupt mask.

IEPINT

Bit 18: IN endpoints interrupt mask.

OEPINT

Bit 19: OUT endpoints interrupt mask.

IISOIXFRM

Bit 20: Incomplete isochronous IN transfer mask.

PXFRM_IISOOXFRM

Bit 21: Incomplete periodic transfer mask.

FSUSPM

Bit 22: Data fetch suspended mask.

PRTIM

Bit 24: Host port interrupt mask.

HCIM

Bit 25: Host channels interrupt mask.

PTXFEM

Bit 26: Periodic TxFIFO empty mask.

CIDSCHGM

Bit 28: Connector ID status change mask.

DISCINT

Bit 29: Disconnect detected interrupt mask.

SRQIM

Bit 30: Session request/new session detected interrupt mask.

WUIM

Bit 31: Resume/remote wakeup detected interrupt mask.

OTG_HS_GRXSTSR_Peripheral

OTG_HS Receive status debug read register (peripheral mode mode)

Offset: 0x1C, reset: 0x0, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRMNUM
r
PKTSTS
r
DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r
BCNT
r
EPNUM
r
Toggle Fields.

EPNUM

Bits 0-3: Endpoint number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

FRMNUM

Bits 21-24: Frame number.

OTG_HS_GRXSTSP_Peripheral

OTG_HS status read and pop register (peripheral mode)

Offset: 0x20, reset: 0x0, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRMNUM
r
PKTSTS
r
DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r
BCNT
r
EPNUM
r
Toggle Fields.

EPNUM

Bits 0-3: Endpoint number.

BCNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

PKTSTS

Bits 17-20: Packet status.

FRMNUM

Bits 21-24: Frame number.

OTG_HS_GRXFSIZ

OTG_HS Receive FIFO size register

Offset: 0x24, reset: 0x00000200, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFD
rw
Toggle Fields.

RXFD

Bits 0-15: RxFIFO depth.

OTG_HS_TX0FSIZ_Peripheral

Endpoint 0 transmit FIFO size (peripheral mode)

Offset: 0x28, reset: 0x00000200, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TX0FD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX0FSA
rw
Toggle Fields.

TX0FSA

Bits 0-15: Endpoint 0 transmit RAM start address.

TX0FD

Bits 16-31: Endpoint 0 TxFIFO depth.

OTG_HS_GNPTXSTS

OTG_HS nonperiodic transmit FIFO/queue status register

Offset: 0x2C, reset: 0x00080200, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXQTOP
r
NPTQXSAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFSAV
r
Toggle Fields.

NPTXFSAV

Bits 0-15: Nonperiodic TxFIFO space available.

NPTQXSAV

Bits 16-23: Nonperiodic transmit request queue space available.

NPTXQTOP

Bits 24-30: Top of the nonperiodic transmit request queue.

OTG_HS_GCCFG

OTG_HS general core configuration register

Offset: 0x38, reset: 0x0, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NOVBUSSENS
rw
SOFOUTEN
rw
VBUSBSEN
rw
VBUSASEN
rw
I2CPADEN
rw
PWRDWN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PWRDWN

Bit 16: Power down.

I2CPADEN

Bit 17: Enable I2C bus connection for the external I2C PHY interface.

VBUSASEN

Bit 18: Enable the VBUS sensing device.

VBUSBSEN

Bit 19: Enable the VBUS sensing device.

SOFOUTEN

Bit 20: SOF output enable.

NOVBUSSENS

Bit 21: VBUS sensing disable option.

OTG_HS_CID

OTG_HS core ID register

Offset: 0x3C, reset: 0x00001200, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRODUCT_ID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRODUCT_ID
rw
Toggle Fields.

PRODUCT_ID

Bits 0-31: Product ID field.

OTG_HS_HPTXFSIZ

OTG_HS Host periodic transmit FIFO size register

Offset: 0x100, reset: 0x02000600, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXSA
rw
Toggle Fields.

PTXSA

Bits 0-15: Host periodic TxFIFO start address.

PTXFD

Bits 16-31: Host periodic TxFIFO depth.

OTG_HS_DIEPTXF1

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x104, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle Fields.

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_HS_DIEPTXF2

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x108, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle Fields.

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_HS_DIEPTXF3

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x11C, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle Fields.

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_HS_DIEPTXF4

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x120, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle Fields.

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_HS_DIEPTXF5

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x124, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle Fields.

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_HS_DIEPTXF6

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x128, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle Fields.

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_HS_DIEPTXF7

OTG_HS device IN endpoint transmit FIFO size register

Offset: 0x12C, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle Fields.

INEPTXSA

Bits 0-15: IN endpoint FIFOx transmit RAM start address.

INEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

OTG_HS_HOST

0x40040400: USB on the go high speed

10/515 fields covered. Toggle Registers.

OTG_HS_HCFG

OTG_HS host configuration register

Offset: 0x0, reset: 0x0, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSLSS
r
FSLSPCS
rw
Toggle Fields.

FSLSPCS

Bits 0-1: FS/LS PHY clock select.

FSLSS

Bit 2: FS- and LS-only support.

OTG_HS_HFIR

OTG_HS Host frame interval register

Offset: 0x4, reset: 0x0000EA60, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRIVL
rw
Toggle Fields.

FRIVL

Bits 0-15: Frame interval.

OTG_HS_HFNUM

OTG_HS host frame number/frame time remaining register

Offset: 0x8, reset: 0x00003FFF, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTREM
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRNUM
r
Toggle Fields.

FRNUM

Bits 0-15: Frame number.

FTREM

Bits 16-31: Frame time remaining.

OTG_HS_HPTXSTS

OTG_HS_Host periodic transmit FIFO/queue status register

Offset: 0x10, reset: 0x00080100, access: Unspecified

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXQTOP
r
PTXQSAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFSAVL
rw
Toggle Fields.

PTXFSAVL

Bits 0-15: Periodic transmit data FIFO space available.

PTXQSAV

Bits 16-23: Periodic transmit request queue space available.

PTXQTOP

Bits 24-31: Top of the periodic transmit request queue.

OTG_HS_HAINT

OTG_HS Host all channels interrupt register

Offset: 0x14, reset: 0x0, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HAINT
r
Toggle Fields.

HAINT

Bits 0-15: Channel interrupts.

OTG_HS_HAINTMSK

OTG_HS host all channels interrupt mask register

Offset: 0x18, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HAINTM
rw
Toggle Fields.

HAINTM

Bits 0-15: Channel interrupt mask.

OTG_HS_HPRT

OTG_HS host port control and status register

Offset: 0x40, reset: 0x0, access: Unspecified

4/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PSPD
r
PTCTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTCTL
rw
PPWR
rw
PLSTS
r
PRST
rw
PSUSP
rw
PRES
rw
POCCHNG
rw
POCA
r
PENCHNG
rw
PENA
rw
PCDET
rw
PCSTS
r
Toggle Fields.

PCSTS

Bit 0: Port connect status.

PCDET

Bit 1: Port connect detected.

PENA

Bit 2: Port enable.

PENCHNG

Bit 3: Port enable/disable change.

POCA

Bit 4: Port overcurrent active.

POCCHNG

Bit 5: Port overcurrent change.

PRES

Bit 6: Port resume.

PSUSP

Bit 7: Port suspend.

PRST

Bit 8: Port reset.

PLSTS

Bits 10-11: Port line status.

PPWR

Bit 12: Port power.

PTCTL

Bits 13-16: Port test control.

PSPD

Bits 17-18: Port speed.

OTG_HS_HCCHAR0

OTG_HS host channel-0 characteristics register

Offset: 0x100, reset: 0x0, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT0

OTG_HS host channel-0 split control register

Offset: 0x104, reset: 0x0, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle Fields.

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT0

OTG_HS host channel-11 interrupt register

Offset: 0x108, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK0

OTG_HS host channel-11 interrupt mask register

Offset: 0x10C, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ0

OTG_HS host channel-11 transfer size register

Offset: 0x110, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA0

OTG_HS host channel-0 DMA address register

Offset: 0x114, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR1

OTG_HS host channel-1 characteristics register

Offset: 0x120, reset: 0x0, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT1

OTG_HS host channel-1 split control register

Offset: 0x124, reset: 0x0, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle Fields.

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT1

OTG_HS host channel-1 interrupt register

Offset: 0x128, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK1

OTG_HS host channel-1 interrupt mask register

Offset: 0x12C, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ1

OTG_HS host channel-1 transfer size register

Offset: 0x130, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA1

OTG_HS host channel-1 DMA address register

Offset: 0x134, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR2

OTG_HS host channel-2 characteristics register

Offset: 0x140, reset: 0x0, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT2

OTG_HS host channel-2 split control register

Offset: 0x144, reset: 0x0, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle Fields.

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT2

OTG_HS host channel-2 interrupt register

Offset: 0x148, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK2

OTG_HS host channel-2 interrupt mask register

Offset: 0x14C, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ2

OTG_HS host channel-2 transfer size register

Offset: 0x150, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA2

OTG_HS host channel-2 DMA address register

Offset: 0x154, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR3

OTG_HS host channel-3 characteristics register

Offset: 0x160, reset: 0x0, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT3

OTG_HS host channel-3 split control register

Offset: 0x164, reset: 0x0, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle Fields.

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT3

OTG_HS host channel-3 interrupt register

Offset: 0x168, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK3

OTG_HS host channel-3 interrupt mask register

Offset: 0x16C, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ3

OTG_HS host channel-3 transfer size register

Offset: 0x170, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA3

OTG_HS host channel-3 DMA address register

Offset: 0x174, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR4

OTG_HS host channel-4 characteristics register

Offset: 0x180, reset: 0x0, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT4

OTG_HS host channel-4 split control register

Offset: 0x184, reset: 0x0, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle Fields.

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT4

OTG_HS host channel-4 interrupt register

Offset: 0x188, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK4

OTG_HS host channel-4 interrupt mask register

Offset: 0x18C, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ4

OTG_HS host channel-4 transfer size register

Offset: 0x190, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA4

OTG_HS host channel-4 DMA address register

Offset: 0x194, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR5

OTG_HS host channel-5 characteristics register

Offset: 0x1A0, reset: 0x0, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT5

OTG_HS host channel-5 split control register

Offset: 0x1A4, reset: 0x0, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle Fields.

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT5

OTG_HS host channel-5 interrupt register

Offset: 0x1A8, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK5

OTG_HS host channel-5 interrupt mask register

Offset: 0x1AC, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ5

OTG_HS host channel-5 transfer size register

Offset: 0x1B0, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA5

OTG_HS host channel-5 DMA address register

Offset: 0x1B4, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR6

OTG_HS host channel-6 characteristics register

Offset: 0x1C0, reset: 0x0, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT6

OTG_HS host channel-6 split control register

Offset: 0x1C4, reset: 0x0, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle Fields.

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT6

OTG_HS host channel-6 interrupt register

Offset: 0x1C8, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK6

OTG_HS host channel-6 interrupt mask register

Offset: 0x1CC, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ6

OTG_HS host channel-6 transfer size register

Offset: 0x1D0, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA6

OTG_HS host channel-6 DMA address register

Offset: 0x1D4, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR7

OTG_HS host channel-7 characteristics register

Offset: 0x1E0, reset: 0x0, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT7

OTG_HS host channel-7 split control register

Offset: 0x1E4, reset: 0x0, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle Fields.

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT7

OTG_HS host channel-7 interrupt register

Offset: 0x1E8, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK7

OTG_HS host channel-7 interrupt mask register

Offset: 0x1EC, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ7

OTG_HS host channel-7 transfer size register

Offset: 0x1F0, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA7

OTG_HS host channel-7 DMA address register

Offset: 0x1F4, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR8

OTG_HS host channel-8 characteristics register

Offset: 0x200, reset: 0x0, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT8

OTG_HS host channel-8 split control register

Offset: 0x204, reset: 0x0, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle Fields.

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT8

OTG_HS host channel-8 interrupt register

Offset: 0x208, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK8

OTG_HS host channel-8 interrupt mask register

Offset: 0x20C, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ8

OTG_HS host channel-8 transfer size register

Offset: 0x210, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA8

OTG_HS host channel-8 DMA address register

Offset: 0x214, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR9

OTG_HS host channel-9 characteristics register

Offset: 0x220, reset: 0x0, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT9

OTG_HS host channel-9 split control register

Offset: 0x224, reset: 0x0, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle Fields.

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT9

OTG_HS host channel-9 interrupt register

Offset: 0x228, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK9

OTG_HS host channel-9 interrupt mask register

Offset: 0x22C, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ9

OTG_HS host channel-9 transfer size register

Offset: 0x230, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA9

OTG_HS host channel-9 DMA address register

Offset: 0x234, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR10

OTG_HS host channel-10 characteristics register

Offset: 0x240, reset: 0x0, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT10

OTG_HS host channel-10 split control register

Offset: 0x244, reset: 0x0, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle Fields.

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT10

OTG_HS host channel-10 interrupt register

Offset: 0x248, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK10

OTG_HS host channel-10 interrupt mask register

Offset: 0x24C, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ10

OTG_HS host channel-10 transfer size register

Offset: 0x250, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA10

OTG_HS host channel-10 DMA address register

Offset: 0x254, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

OTG_HS_HCCHAR11

OTG_HS host channel-11 characteristics register

Offset: 0x260, reset: 0x0, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw
CHDIS
rw
ODDFRM
rw
DAD
rw
MC
rw
EPTYP
rw
LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw
EPNUM
rw
MPSIZ
rw
Toggle Fields.

MPSIZ

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSDEV

Bit 17: Low-speed device.

EPTYP

Bits 18-19: Endpoint type.

MC

Bits 20-21: Multi Count (MC) / Error Count (EC).

DAD

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CHDIS

Bit 30: Channel disable.

CHENA

Bit 31: Channel enable.

OTG_HS_HCSPLT11

OTG_HS host channel-11 split control register

Offset: 0x264, reset: 0x0, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw
COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw
HUBADDR
rw
PRTADDR
rw
Toggle Fields.

PRTADDR

Bits 0-6: Port address.

HUBADDR

Bits 7-13: Hub address.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: Do complete split.

SPLITEN

Bit 31: Split enable.

OTG_HS_HCINT11

OTG_HS host channel-11 interrupt register

Offset: 0x268, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERR
rw
FRMOR
rw
BBERR
rw
TXERR
rw
NYET
rw
ACK
rw
NAK
rw
STALL
rw
AHBERR
rw
CHH
rw
XFRC
rw
Toggle Fields.

XFRC

Bit 0: Transfer completed.

CHH

Bit 1: Channel halted.

AHBERR

Bit 2: AHB error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: Response received interrupt.

TXERR

Bit 7: Transaction error.

BBERR

Bit 8: Babble error.

FRMOR

Bit 9: Frame overrun.

DTERR

Bit 10: Data toggle error.

OTG_HS_HCINTMSK11

OTG_HS host channel-11 interrupt mask register

Offset: 0x26C, reset: 0x0, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERRM
rw
FRMORM
rw
BBERRM
rw
TXERRM
rw
NYET
rw
ACKM
rw
NAKM
rw
STALLM
rw
AHBERR
rw
CHHM
rw
XFRCM
rw
Toggle Fields.

XFRCM

Bit 0: Transfer completed mask.

CHHM

Bit 1: Channel halted mask.

AHBERR

Bit 2: AHB error.

STALLM

Bit 3: STALL response received interrupt mask.

NAKM

Bit 4: NAK response received interrupt mask.

ACKM

Bit 5: ACK response received/transmitted interrupt mask.

NYET

Bit 6: response received interrupt mask.

TXERRM

Bit 7: Transaction error mask.

BBERRM

Bit 8: Babble error mask.

FRMORM

Bit 9: Frame overrun mask.

DTERRM

Bit 10: Data toggle error mask.

OTG_HS_HCTSIZ11

OTG_HS host channel-11 transfer size register

Offset: 0x270, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw
PKTCNT
rw
XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle Fields.

XFRSIZ

Bits 0-18: Transfer size.

PKTCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

OTG_HS_HCDMA11

OTG_HS host channel-11 DMA address register

Offset: 0x274, reset: 0x0, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

OTG_HS_PWRCLK

0x40040E00: USB on the go high speed

0/3 fields covered. Toggle Registers.

OTG_HS_PCGCR

Power and clock gating control register

Offset: 0x0, reset: 0x0, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYSUSP
rw
GATEHCLK
rw
STPPCLK
rw
Toggle Fields.

STPPCLK

Bit 0: Stop PHY clock.

GATEHCLK

Bit 1: Gate HCLK.

PHYSUSP

Bit 4: PHY suspended.

PWR

0x40007000: Power control

5/14 fields covered. Toggle Registers.

CR

power control register

Offset: 0x0, reset: 0x00000000, access: read-write

1/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPDS
rw
DBP
rw
PLS
rw
PVDE
rw
CSBF
rw
CWUF
rw
PDDS
rw
LPDS
rw
Toggle Fields.

LPDS

Bit 0: Low-power deep sleep.

PDDS

Bit 1: Power down deepsleep.

Allowed values:
0: STOP_MODE: Enter Stop mode when the CPU enters deepsleep
1: STANDBY_MODE: Enter Standby mode when the CPU enters deepsleep

CWUF

Bit 2: Clear wakeup flag.

CSBF

Bit 3: Clear standby flag.

PVDE

Bit 4: Power voltage detector enable.

PLS

Bits 5-7: PVD level selection.

DBP

Bit 8: Disable backup domain write protection.

FPDS

Bit 9: Flash power down in Stop mode.

CSR

power control/status register

Offset: 0x4, reset: 0x00000000, access: Unspecified

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRE
rw
EWUP
rw
BRR
r
PVDO
r
SBF
r
WUF
r
Toggle Fields.

WUF

Bit 0: Wakeup flag.

SBF

Bit 1: Standby flag.

PVDO

Bit 2: PVD output.

BRR

Bit 3: Backup regulator ready.

EWUP

Bit 8: Enable WKUP pin.

BRE

Bit 9: Backup regulator enable.

RCC

0x40023800: Reset and clock control

249/249 fields covered. Toggle Registers.

CR

clock control register

Offset: 0x0, reset: 0x00000083, access: Unspecified

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLI2SRDY
r
PLLI2SON
rw
PLLRDY
r
PLLON
rw
CSSON
rw
HSEBYP
rw
HSERDY
r
HSEON
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSICAL
r
HSITRIM
rw
HSIRDY
r
HSION
rw
Toggle Fields.

HSION

Bit 0: Internal high-speed clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSIRDY

Bit 1: Internal high-speed clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSITRIM

Bits 3-7: Internal high-speed clock trimming.

Allowed values: 0-31

HSICAL

Bits 8-15: Internal high-speed clock calibration.

Allowed values: 0-255

HSEON

Bit 16: HSE clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSERDY

Bit 17: HSE clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSEBYP

Bit 18: HSE clock bypass.

Allowed values:
0: NotBypassed: HSE crystal oscillator not bypassed
1: Bypassed: HSE crystal oscillator bypassed with external clock

CSSON

Bit 19: Clock security system enable.

Allowed values:
0: Off: Clock security system disabled (clock detector OFF)
1: On: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)

PLLON

Bit 24: Main PLL (PLL) enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLLRDY

Bit 25: Main PLL (PLL) clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PLLI2SON

Bit 26: PLLI2S enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLLI2SRDY

Bit 27: PLLI2S clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PLLCFGR

PLL configuration register

Offset: 0x4, reset: 0x24003010, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLQ
rw
PLLSRC
rw
PLLP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLN
rw
PLLM
rw
Toggle Fields.

PLLM

Bits 0-5: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock.

Allowed values: 2-63

PLLN

Bits 6-14: Main PLL (PLL) multiplication factor for VCO.

Allowed values: 50-432

PLLP

Bits 16-17: Main PLL (PLL) division factor for main system clock.

Allowed values:
0: Div2: PLLP=2
1: Div4: PLLP=4
2: Div6: PLLP=6
3: Div8: PLLP=8

PLLSRC

Bit 22: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source.

Allowed values:
0: HSI: HSI clock selected as PLL and PLLI2S clock entry
1: HSE: HSE oscillator clock selected as PLL and PLLI2S clock entry

PLLQ

Bits 24-27: Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks.

Allowed values: 2-15

CFGR

clock configuration register

Offset: 0x8, reset: 0x00000000, access: Unspecified

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCO2
N/A
MCO2PRE
N/A
MCO1PRE
N/A
I2SSRC
rw
MCO1
N/A
RTCPRE
N/A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PPRE2
N/A
PPRE1
N/A
HPRE
N/A
SWS
N/A
SW
N/A
Toggle Fields.

SW

Bits 0-1: System clock switch.

Allowed values:
0: HSI: HSI selected as system clock
1: HSE: HSE selected as system clock
2: PLL: PLL selected as system clock

SWS

Bits 2-3: System clock switch status.

Allowed values:
0: HSI: HSI oscillator used as system clock
1: HSE: HSE oscillator used as system clock
2: PLL: PLL used as system clock

HPRE

Bits 4-7: AHB prescaler.

Allowed values:
0: Div1: SYSCLK not divided
8: Div2: SYSCLK divided by 2
9: Div4: SYSCLK divided by 4
10: Div8: SYSCLK divided by 8
11: Div16: SYSCLK divided by 16
12: Div64: SYSCLK divided by 64
13: Div128: SYSCLK divided by 128
14: Div256: SYSCLK divided by 256
15: Div512: SYSCLK divided by 512

PPRE1

Bits 10-12: APB Low speed prescaler (APB1).

Allowed values:
0: Div1: HCLK not divided
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16

PPRE2

Bits 13-15: APB high-speed prescaler (APB2).

Allowed values:
0: Div1: HCLK not divided
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16

RTCPRE

Bits 16-20: HSE division factor for RTC clock.

Allowed values: 0-31

MCO1

Bits 21-22: Microcontroller clock output 1.

Allowed values:
0: HSI: HSI clock selected
1: LSE: LSE oscillator selected
2: HSE: HSE oscillator clock selected
3: PLL: PLL clock selected

I2SSRC

Bit 23: I2S clock selection.

Allowed values:
0: PLLI2S: PLLI2S clock used as I2S clock source
1: CKIN: External clock mapped on the I2S_CKIN pin used as I2S clock source

MCO1PRE

Bits 24-26: MCO1 prescaler.

Allowed values:
0: Div1: No division
4: Div2: Division by 2
5: Div3: Division by 3
6: Div4: Division by 4
7: Div5: Division by 5

MCO2PRE

Bits 27-29: MCO2 prescaler.

Allowed values:
0: Div1: No division
4: Div2: Division by 2
5: Div3: Division by 3
6: Div4: Division by 4
7: Div5: Division by 5

MCO2

Bits 30-31: Microcontroller clock output 2.

Allowed values:
0: SYSCLK: System clock (SYSCLK) selected
1: PLLI2S: PLLI2S clock selected
2: HSE: HSE oscillator clock selected
3: PLL: PLL clock selected

CIR

clock interrupt register

Offset: 0xC, reset: 0x00000000, access: Unspecified

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSSC
w
PLLI2SRDYC
w
PLLRDYC
w
HSERDYC
w
HSIRDYC
w
LSERDYC
w
LSIRDYC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLI2SRDYIE
rw
PLLRDYIE
rw
HSERDYIE
rw
HSIRDYIE
rw
LSERDYIE
rw
LSIRDYIE
rw
CSSF
r
PLLI2SRDYF
r
PLLRDYF
r
HSERDYF
r
HSIRDYF
r
LSERDYF
r
LSIRDYF
r
Toggle Fields.

LSIRDYF

Bit 0: LSI ready interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

LSERDYF

Bit 1: LSE ready interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

HSIRDYF

Bit 2: HSI ready interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

HSERDYF

Bit 3: HSE ready interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

PLLRDYF

Bit 4: Main PLL (PLL) ready interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

PLLI2SRDYF

Bit 5: PLLI2S ready interrupt flag.

Allowed values:
0: NotInterrupted: No clock ready interrupt
1: Interrupted: Clock ready interrupt

CSSF

Bit 7: Clock security system interrupt flag.

Allowed values:
0: NotInterrupted: No clock security interrupt caused by HSE clock failure
1: Interrupted: Clock security interrupt caused by HSE clock failure

LSIRDYIE

Bit 8: LSI ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LSERDYIE

Bit 9: LSE ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HSIRDYIE

Bit 10: HSI ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HSERDYIE

Bit 11: HSE ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

PLLRDYIE

Bit 12: Main PLL (PLL) ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

PLLI2SRDYIE

Bit 13: PLLI2S ready interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LSIRDYC

Bit 16: LSI ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

LSERDYC

Bit 17: LSE ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

HSIRDYC

Bit 18: HSI ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

HSERDYC

Bit 19: HSE ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

PLLRDYC

Bit 20: Main PLL(PLL) ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

PLLI2SRDYC

Bit 21: PLLI2S ready interrupt clear.

Allowed values:
1: Clear: Clear interrupt flag

CSSC

Bit 23: Clock security system interrupt clear.

Allowed values:
1: Clear: Clear CSSF flag

AHB1RSTR

AHB1 peripheral reset register

Offset: 0x10, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTGHSRST
rw
ETHMACRST
rw
DMA2RST
rw
DMA1RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCRST
rw
GPIOIRST
rw
GPIOHRST
rw
GPIOGRST
rw
GPIOFRST
rw
GPIOERST
rw
GPIODRST
rw
GPIOCRST
rw
GPIOBRST
rw
GPIOARST
rw
Toggle Fields.

GPIOARST

Bit 0: IO port A reset.

Allowed values:
1: Reset: Reset the selected module

GPIOBRST

Bit 1: IO port B reset.

Allowed values:
1: Reset: Reset the selected module

GPIOCRST

Bit 2: IO port C reset.

Allowed values:
1: Reset: Reset the selected module

GPIODRST

Bit 3: IO port D reset.

Allowed values:
1: Reset: Reset the selected module

GPIOERST

Bit 4: IO port E reset.

Allowed values:
1: Reset: Reset the selected module

GPIOFRST

Bit 5: IO port F reset.

Allowed values:
1: Reset: Reset the selected module

GPIOGRST

Bit 6: IO port G reset.

Allowed values:
1: Reset: Reset the selected module

GPIOHRST

Bit 7: IO port H reset.

Allowed values:
1: Reset: Reset the selected module

GPIOIRST

Bit 8: IO port I reset.

Allowed values:
1: Reset: Reset the selected module

CRCRST

Bit 12: CRC reset.

Allowed values:
1: Reset: Reset the selected module

DMA1RST

Bit 21: DMA2 reset.

Allowed values:
1: Reset: Reset the selected module

DMA2RST

Bit 22: DMA2 reset.

Allowed values:
1: Reset: Reset the selected module

ETHMACRST

Bit 25: Ethernet MAC reset.

Allowed values:
1: Reset: Reset the selected module

OTGHSRST

Bit 29: USB OTG HS module reset.

Allowed values:
1: Reset: Reset the selected module

AHB2RSTR

AHB2 peripheral reset register

Offset: 0x14, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTGFSRST
rw
RNGRST
rw
HSAHRST
rw
CRYPRST
rw
DCMIRST
rw
Toggle Fields.

DCMIRST

Bit 0: Camera interface reset.

Allowed values:
1: Reset: Reset the selected module

CRYPRST

Bit 4: Cryptographic module reset.

Allowed values:
1: Reset: Reset the selected module

HSAHRST

Bit 5: Hash module reset.

Allowed values:
1: Reset: Reset the selected module

RNGRST

Bit 6: Random number generator module reset.

Allowed values:
1: Reset: Reset the selected module

OTGFSRST

Bit 7: USB OTG FS module reset.

Allowed values:
1: Reset: Reset the selected module

AHB3RSTR

AHB3 peripheral reset register

Offset: 0x18, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSMCRST
rw
Toggle Fields.

FSMCRST

Bit 0: Flexible static memory controller module reset.

Allowed values:
1: Reset: Reset the selected module

APB1RSTR

APB1 peripheral reset register

Offset: 0x20, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACRST
rw
PWRRST
rw
CAN2RST
rw
CAN1RST
rw
I2C3RST
rw
I2C2RST
rw
I2C1RST
rw
UART5RST
rw
UART4RST
rw
UART3RST
rw
UART2RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3RST
rw
SPI2RST
rw
WWDGRST
rw
TIM14RST
rw
TIM13RST
rw
TIM12RST
rw
TIM7RST
rw
TIM6RST
rw
TIM5RST
rw
TIM4RST
rw
TIM3RST
rw
TIM2RST
rw
Toggle Fields.

TIM2RST

Bit 0: TIM2 reset.

Allowed values:
1: Reset: Reset the selected module

TIM3RST

Bit 1: TIM3 reset.

Allowed values:
1: Reset: Reset the selected module

TIM4RST

Bit 2: TIM4 reset.

Allowed values:
1: Reset: Reset the selected module

TIM5RST

Bit 3: TIM5 reset.

Allowed values:
1: Reset: Reset the selected module

TIM6RST

Bit 4: TIM6 reset.

Allowed values:
1: Reset: Reset the selected module

TIM7RST

Bit 5: TIM7 reset.

Allowed values:
1: Reset: Reset the selected module

TIM12RST

Bit 6: TIM12 reset.

Allowed values:
1: Reset: Reset the selected module

TIM13RST

Bit 7: TIM13 reset.

Allowed values:
1: Reset: Reset the selected module

TIM14RST

Bit 8: TIM14 reset.

Allowed values:
1: Reset: Reset the selected module

WWDGRST

Bit 11: Window watchdog reset.

Allowed values:
1: Reset: Reset the selected module

SPI2RST

Bit 14: SPI 2 reset.

Allowed values:
1: Reset: Reset the selected module

SPI3RST

Bit 15: SPI 3 reset.

Allowed values:
1: Reset: Reset the selected module

UART2RST

Bit 17: USART 2 reset.

Allowed values:
1: Reset: Reset the selected module

UART3RST

Bit 18: USART 3 reset.

Allowed values:
1: Reset: Reset the selected module

UART4RST

Bit 19: USART 4 reset.

Allowed values:
1: Reset: Reset the selected module

UART5RST

Bit 20: USART 5 reset.

Allowed values:
1: Reset: Reset the selected module

I2C1RST

Bit 21: I2C 1 reset.

Allowed values:
1: Reset: Reset the selected module

I2C2RST

Bit 22: I2C 2 reset.

Allowed values:
1: Reset: Reset the selected module

I2C3RST

Bit 23: I2C3 reset.

Allowed values:
1: Reset: Reset the selected module

CAN1RST

Bit 25: CAN1 reset.

Allowed values:
1: Reset: Reset the selected module

CAN2RST

Bit 26: CAN2 reset.

Allowed values:
1: Reset: Reset the selected module

PWRRST

Bit 28: Power interface reset.

Allowed values:
1: Reset: Reset the selected module

DACRST

Bit 29: DAC reset.

Allowed values:
1: Reset: Reset the selected module

APB2RSTR

APB2 peripheral reset register

Offset: 0x24, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIM11RST
rw
TIM10RST
rw
TIM9RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSCFGRST
rw
SPI1RST
rw
SDIORST
rw
ADCRST
rw
USART6RST
rw
USART1RST
rw
TIM8RST
rw
TIM1RST
rw
Toggle Fields.

TIM1RST

Bit 0: TIM1 reset.

Allowed values:
1: Reset: Reset the selected module

TIM8RST

Bit 1: TIM8 reset.

Allowed values:
1: Reset: Reset the selected module

USART1RST

Bit 4: USART1 reset.

Allowed values:
1: Reset: Reset the selected module

USART6RST

Bit 5: USART6 reset.

Allowed values:
1: Reset: Reset the selected module

ADCRST

Bit 8: ADC interface reset (common to all ADCs).

Allowed values:
1: Reset: Reset the selected module

SDIORST

Bit 11: SDIO reset.

Allowed values:
1: Reset: Reset the selected module

SPI1RST

Bit 12: SPI 1 reset.

Allowed values:
1: Reset: Reset the selected module

SYSCFGRST

Bit 14: System configuration controller reset.

Allowed values:
1: Reset: Reset the selected module

TIM9RST

Bit 16: TIM9 reset.

Allowed values:
1: Reset: Reset the selected module

TIM10RST

Bit 17: TIM10 reset.

Allowed values:
1: Reset: Reset the selected module

TIM11RST

Bit 18: TIM11 reset.

Allowed values:
1: Reset: Reset the selected module

AHB1ENR

AHB1 peripheral clock register

Offset: 0x30, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTGHSULPIEN
rw
OTGHSEN
rw
ETHMACPTPEN
rw
ETHMACRXEN
rw
ETHMACTXEN
rw
ETHMACEN
rw
DMA2EN
rw
DMA1EN
rw
BKPSRAMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCEN
rw
GPIOIEN
rw
GPIOHEN
rw
GPIOGEN
rw
GPIOFEN
rw
GPIOEEN
rw
GPIODEN
rw
GPIOCEN
rw
GPIOBEN
rw
GPIOAEN
rw
Toggle Fields.

GPIOAEN

Bit 0: IO port A clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOBEN

Bit 1: IO port B clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOCEN

Bit 2: IO port C clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIODEN

Bit 3: IO port D clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOEEN

Bit 4: IO port E clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOFEN

Bit 5: IO port F clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOGEN

Bit 6: IO port G clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOHEN

Bit 7: IO port H clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOIEN

Bit 8: IO port I clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CRCEN

Bit 12: CRC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

BKPSRAMEN

Bit 18: Backup SRAM interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DMA1EN

Bit 21: DMA1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DMA2EN

Bit 22: DMA2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ETHMACEN

Bit 25: Ethernet MAC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ETHMACTXEN

Bit 26: Ethernet Transmission clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ETHMACRXEN

Bit 27: Ethernet Reception clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ETHMACPTPEN

Bit 28: Ethernet PTP clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OTGHSEN

Bit 29: USB OTG HS clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OTGHSULPIEN

Bit 30: USB OTG HSULPI clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB2ENR

AHB2 peripheral clock enable register

Offset: 0x34, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTGFSEN
rw
RNGEN
rw
HASHEN
rw
CRYPEN
rw
DCMIEN
rw
Toggle Fields.

DCMIEN

Bit 0: Camera interface enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CRYPEN

Bit 4: Cryptographic modules clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

HASHEN

Bit 5: Hash modules clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

RNGEN

Bit 6: Random number generator clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OTGFSEN

Bit 7: USB OTG FS clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB3ENR

AHB3 peripheral clock enable register

Offset: 0x38, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSMCEN
rw
Toggle Fields.

FSMCEN

Bit 0: Flexible static memory controller module clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB1ENR

APB1 peripheral clock enable register

Offset: 0x40, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACEN
rw
PWREN
rw
CAN2EN
rw
CAN1EN
rw
I2C3EN
rw
I2C2EN
rw
I2C1EN
rw
UART5EN
rw
UART4EN
rw
USART3EN
rw
USART2EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3EN
rw
SPI2EN
rw
WWDGEN
rw
TIM14EN
rw
TIM13EN
rw
TIM12EN
rw
TIM7EN
rw
TIM6EN
rw
TIM5EN
rw
TIM4EN
rw
TIM3EN
rw
TIM2EN
rw
Toggle Fields.

TIM2EN

Bit 0: TIM2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM3EN

Bit 1: TIM3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM4EN

Bit 2: TIM4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM5EN

Bit 3: TIM5 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM6EN

Bit 4: TIM6 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM7EN

Bit 5: TIM7 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM12EN

Bit 6: TIM12 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM13EN

Bit 7: TIM13 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM14EN

Bit 8: TIM14 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

WWDGEN

Bit 11: Window watchdog clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI2EN

Bit 14: SPI2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI3EN

Bit 15: SPI3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART2EN

Bit 17: USART 2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART3EN

Bit 18: USART3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART4EN

Bit 19: UART4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART5EN

Bit 20: UART5 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C1EN

Bit 21: I2C1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C2EN

Bit 22: I2C2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C3EN

Bit 23: I2C3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CAN1EN

Bit 25: CAN 1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CAN2EN

Bit 26: CAN 2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PWREN

Bit 28: Power interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DACEN

Bit 29: DAC interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB2ENR

APB2 peripheral clock enable register

Offset: 0x44, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIM11EN
rw
TIM10EN
rw
TIM9EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSCFGEN
rw
SPI1EN
rw
SDIOEN
rw
ADC3EN
rw
ADC2EN
rw
ADC1EN
rw
USART6EN
rw
USART1EN
rw
TIM8EN
rw
TIM1EN
rw
Toggle Fields.

TIM1EN

Bit 0: TIM1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM8EN

Bit 1: TIM8 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART1EN

Bit 4: USART1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART6EN

Bit 5: USART6 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADC1EN

Bit 8: ADC1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADC2EN

Bit 9: ADC2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADC3EN

Bit 10: ADC3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SDIOEN

Bit 11: SDIO clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI1EN

Bit 12: SPI1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SYSCFGEN

Bit 14: System configuration controller clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM9EN

Bit 16: TIM9 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM10EN

Bit 17: TIM10 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM11EN

Bit 18: TIM11 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB1LPENR

AHB1 peripheral clock enable in low power mode register

Offset: 0x50, reset: 0x7E6791FF, access: read-write

22/22 fields covered.

GPIOALPEN

Bit 0: IO port A clock enable during sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

GPIOBLPEN

Bit 1: IO port B clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

GPIOCLPEN

Bit 2: IO port C clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

GPIODLPEN

Bit 3: IO port D clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

GPIOELPEN

Bit 4: IO port E clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

GPIOFLPEN

Bit 5: IO port F clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

GPIOGLPEN

Bit 6: IO port G clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

GPIOHLPEN

Bit 7: IO port H clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

GPIOILPEN

Bit 8: IO port I clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

CRCLPEN

Bit 12: CRC clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

FLITFLPEN

Bit 15: Flash interface clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

SRAM1LPEN

Bit 16: SRAM 1interface clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

SRAM2LPEN

Bit 17: SRAM 2 interface clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

BKPSRAMLPEN

Bit 18: Backup SRAM interface clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

DMA1LPEN

Bit 21: DMA1 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

DMA2LPEN

Bit 22: DMA2 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

ETHMACLPEN

Bit 25: Ethernet MAC clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

ETHMACTXLPEN

Bit 26: Ethernet transmission clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

ETHMACRXLPEN

Bit 27: Ethernet reception clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

ETHMACPTPLPEN

Bit 28: Ethernet PTP clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

OTGHSLPEN

Bit 29: USB OTG HS clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

OTGHSULPILPEN

Bit 30: USB OTG HS ULPI clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

AHB2LPENR

AHB2 peripheral clock enable in low power mode register

Offset: 0x54, reset: 0x000000F1, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTGFSLPEN
rw
RNGLPEN
rw
HASHLPEN
rw
CRYPLPEN
rw
DCMILPEN
rw
Toggle Fields.

DCMILPEN

Bit 0: Camera interface enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

CRYPLPEN

Bit 4: Cryptography modules clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

HASHLPEN

Bit 5: Hash modules clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

RNGLPEN

Bit 6: Random number generator clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

OTGFSLPEN

Bit 7: USB OTG FS clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

AHB3LPENR

AHB3 peripheral clock enable in low power mode register

Offset: 0x58, reset: 0x00000001, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSMCLPEN
rw
Toggle Fields.

FSMCLPEN

Bit 0: Flexible static memory controller module clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

APB1LPENR

APB1 peripheral clock enable in low power mode register

Offset: 0x60, reset: 0x36FEC9FF, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACLPEN
rw
PWRLPEN
rw
CAN2LPEN
rw
CAN1LPEN
rw
I2C3LPEN
rw
I2C2LPEN
rw
I2C1LPEN
rw
UART5LPEN
rw
UART4LPEN
rw
USART3LPEN
rw
USART2LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3LPEN
rw
SPI2LPEN
rw
WWDGLPEN
rw
TIM14LPEN
rw
TIM13LPEN
rw
TIM12LPEN
rw
TIM7LPEN
rw
TIM6LPEN
rw
TIM5LPEN
rw
TIM4LPEN
rw
TIM3LPEN
rw
TIM2LPEN
rw
Toggle Fields.

TIM2LPEN

Bit 0: TIM2 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM3LPEN

Bit 1: TIM3 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM4LPEN

Bit 2: TIM4 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM5LPEN

Bit 3: TIM5 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM6LPEN

Bit 4: TIM6 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM7LPEN

Bit 5: TIM7 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM12LPEN

Bit 6: TIM12 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM13LPEN

Bit 7: TIM13 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM14LPEN

Bit 8: TIM14 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

WWDGLPEN

Bit 11: Window watchdog clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

SPI2LPEN

Bit 14: SPI2 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

SPI3LPEN

Bit 15: SPI3 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

USART2LPEN

Bit 17: USART2 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

USART3LPEN

Bit 18: USART3 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

UART4LPEN

Bit 19: UART4 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

UART5LPEN

Bit 20: UART5 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

I2C1LPEN

Bit 21: I2C1 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

I2C2LPEN

Bit 22: I2C2 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

I2C3LPEN

Bit 23: I2C3 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

CAN1LPEN

Bit 25: CAN 1 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

CAN2LPEN

Bit 26: CAN 2 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

PWRLPEN

Bit 28: Power interface clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

DACLPEN

Bit 29: DAC interface clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

APB2LPENR

APB2 peripheral clock enabled in low power mode register

Offset: 0x64, reset: 0x00075F33, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIM11LPEN
rw
TIM10LPEN
rw
TIM9LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSCFGLPEN
rw
SPI1LPEN
rw
SDIOLPEN
rw
ADC3LPEN
rw
ADC2LPEN
rw
ADC1LPEN
rw
USART6LPEN
rw
USART1LPEN
rw
TIM8LPEN
rw
TIM1LPEN
rw
Toggle Fields.

TIM1LPEN

Bit 0: TIM1 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM8LPEN

Bit 1: TIM8 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

USART1LPEN

Bit 4: USART1 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

USART6LPEN

Bit 5: USART6 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

ADC1LPEN

Bit 8: ADC1 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

ADC2LPEN

Bit 9: ADC2 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

ADC3LPEN

Bit 10: ADC 3 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

SDIOLPEN

Bit 11: SDIO clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

SPI1LPEN

Bit 12: SPI 1 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

SYSCFGLPEN

Bit 14: System configuration controller clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM9LPEN

Bit 16: TIM9 clock enable during sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM10LPEN

Bit 17: TIM10 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

TIM11LPEN

Bit 18: TIM11 clock enable during Sleep mode.

Allowed values:
0: DisabledInSleep: Selected module is disabled during Sleep mode
1: EnabledInSleep: Selected module is enabled during Sleep mode

BDCR

Backup domain control register

Offset: 0x70, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BDRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw
RTCSEL
N/A
LSEBYP
rw
LSERDY
r
LSEON
rw
Toggle Fields.

LSEON

Bit 0: External low-speed oscillator enable.

Allowed values:
0: Off: LSE oscillator Off
1: On: LSE oscillator On

LSERDY

Bit 1: External low-speed oscillator ready.

Allowed values:
0: NotReady: LSE oscillator not ready
1: Ready: LSE oscillator ready

LSEBYP

Bit 2: External low-speed oscillator bypass.

Allowed values:
0: NotBypassed: LSE crystal oscillator not bypassed
1: Bypassed: LSE crystal oscillator bypassed with external clock

RTCSEL

Bits 8-9: RTC clock source selection.

Allowed values:
0: NoClock: No clock
1: LSE: LSE oscillator clock used as RTC clock
2: LSI: LSI oscillator clock used as RTC clock
3: HSE: HSE oscillator clock divided by a prescaler used as RTC clock

RTCEN

Bit 15: RTC clock enable.

Allowed values:
0: Disabled: RTC clock disabled
1: Enabled: RTC clock enabled

BDRST

Bit 16: Backup domain software reset.

Allowed values:
0: Disabled: Reset not activated
1: Enabled: Reset the entire RTC domain

CSR

clock control & status register

Offset: 0x74, reset: 0x0E000000, access: Unspecified

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWRRSTF
rw
WWDGRSTF
rw
WDGRSTF
rw
SFTRSTF
rw
PORRSTF
rw
PADRSTF
rw
BORRSTF
rw
RMVF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSIRDY
r
LSION
rw
Toggle Fields.

LSION

Bit 0: Internal low-speed oscillator enable.

Allowed values:
0: Off: LSI oscillator Off
1: On: LSI oscillator On

LSIRDY

Bit 1: Internal low-speed oscillator ready.

Allowed values:
0: NotReady: LSI oscillator not ready
1: Ready: LSI oscillator ready

RMVF

Bit 24: Remove reset flag.

Allowed values:
1: Clear: Clears the reset flag

BORRSTF

Bit 25: BOR reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

PADRSTF

Bit 26: PIN reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

PORRSTF

Bit 27: POR/PDR reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

SFTRSTF

Bit 28: Software reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

WDGRSTF

Bit 29: Independent watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

WWDGRSTF

Bit 30: Window watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

LPWRRSTF

Bit 31: Low-power reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

SSCGR

spread spectrum clock generation register

Offset: 0x80, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSCGEN
rw
SPREADSEL
rw
INCSTEP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INCSTEP
rw
MODPER
rw
Toggle Fields.

MODPER

Bits 0-12: Modulation period.

Allowed values: 0-8191

INCSTEP

Bits 13-27: Incrementation step.

Allowed values: 0-32767

SPREADSEL

Bit 30: Spread Select.

Allowed values:
0: Center: Center spread
1: Down: Down spread

SSCGEN

Bit 31: Spread spectrum modulation enable.

Allowed values:
0: Disabled: Spread spectrum modulation disabled
1: Enabled: Spread spectrum modulation enabled

PLLI2SCFGR

PLLI2S configuration register

Offset: 0x84, reset: 0x20003000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLI2SR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLI2SN
rw
Toggle Fields.

PLLI2SN

Bits 6-14: PLLI2S multiplication factor for VCO.

Allowed values: 50-432

PLLI2SR

Bits 28-30: PLLI2S division factor for I2S clocks.

Allowed values: 2-7

RNG

0x50060800: Random number generator

4/8 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IE
rw
RNGEN
rw
Toggle Fields.

RNGEN

Bit 2: Random number generator enable.

IE

Bit 3: Interrupt enable.

SR

status register

Offset: 0x4, reset: 0x00000000, access: Unspecified

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEIS
rw
CEIS
rw
SECS
r
CECS
r
DRDY
r
Toggle Fields.

DRDY

Bit 0: Data ready.

CECS

Bit 1: Clock error current status.

SECS

Bit 2: Seed error current status.

CEIS

Bit 5: Clock error interrupt status.

SEIS

Bit 6: Seed error interrupt status.

DR

data register

Offset: 0x8, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNDATA
r
Toggle Fields.

RNDATA

Bits 0-31: Random data.

RTC

0x40002800: Real-time clock

17/99 fields covered. Toggle Registers.

TR

time register

Offset: 0x0, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw
MNU
rw
ST
rw
SU
rw
Toggle Fields.

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

DR

date register

Offset: 0x4, reset: 0x00002101, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw
YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw
MT
rw
MU
rw
DT
rw
DU
rw
Toggle Fields.

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

CR

control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COE
rw
OSEL
rw
POL
rw
BKP
rw
SUB1H
rw
ADD1H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIE
rw
WUTIE
rw
ALRBIE
rw
ALRAIE
rw
TSE
rw
WUTE
rw
ALRBE
rw
ALRAE
rw
DCE
rw
FMT
rw
REFCKON
rw
TSEDGE
rw
WUCKSEL
rw
Toggle Fields.

WUCKSEL

Bits 0-2: Wakeup clock selection.

TSEDGE

Bit 3: Time-stamp event active edge.

REFCKON

Bit 4: Reference clock detection enable (50 or 60 Hz).

FMT

Bit 6: Hour format.

DCE

Bit 7: Coarse digital calibration enable.

ALRAE

Bit 8: Alarm A enable.

ALRBE

Bit 9: Alarm B enable.

WUTE

Bit 10: Wakeup timer enable.

TSE

Bit 11: Time stamp enable.

ALRAIE

Bit 12: Alarm A interrupt enable.

ALRBIE

Bit 13: Alarm B interrupt enable.

WUTIE

Bit 14: Wakeup timer interrupt enable.

TSIE

Bit 15: Time-stamp interrupt enable.

ADD1H

Bit 16: Add 1 hour (summer time change).

SUB1H

Bit 17: Subtract 1 hour (winter time change).

BKP

Bit 18: Backup.

POL

Bit 20: Output polarity.

OSEL

Bits 21-22: Output selection.

COE

Bit 23: Calibration output enable.

ISR

initialization and status register

Offset: 0xC, reset: 0x00000007, access: Unspecified

5/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP1F
rw
TSOVF
rw
TSF
rw
WUTF
rw
ALRBF
rw
ALRAF
rw
INIT
rw
INITF
r
RSF
rw
INITS
r
WUTWF
r
ALRBWF
r
ALRAWF
r
Toggle Fields.

ALRAWF

Bit 0: Alarm A write flag.

ALRBWF

Bit 1: Alarm B write flag.

WUTWF

Bit 2: Wakeup timer write flag.

INITS

Bit 4: Initialization status flag.

RSF

Bit 5: Registers synchronization flag.

INITF

Bit 6: Initialization flag.

INIT

Bit 7: Initialization mode.

ALRAF

Bit 8: Alarm A flag.

ALRBF

Bit 9: Alarm B flag.

WUTF

Bit 10: Wakeup timer flag.

TSF

Bit 11: Time-stamp flag.

TSOVF

Bit 12: Time-stamp overflow flag.

TAMP1F

Bit 13: Tamper detection flag.

PRER

prescaler register

Offset: 0x10, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PREDIV_A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREDIV_S
rw
Toggle Fields.

PREDIV_S

Bits 0-12: Synchronous prescaler factor.

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

WUTR

wakeup timer register

Offset: 0x14, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUT
rw
Toggle Fields.

WUT

Bits 0-15: Wakeup auto-reload value bits.

CALIBR

calibration register

Offset: 0x18, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCS
rw
DC
rw
Toggle Fields.

DC

Bits 0-4: Digital calibration.

DCS

Bit 7: Digital calibration sign.

ALRMAR

alarm A register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw
WDSEL
rw
DT
rw
DU
rw
MSK3
rw
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw
MNT
rw
MNU
rw
MSK1
rw
ST
rw
SU
rw
Toggle Fields.

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm A seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm A minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm A hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm A date mask.

ALRMBR

alarm B register

Offset: 0x20, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw
WDSEL
rw
DT
rw
DU
rw
MSK3
rw
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw
MNT
rw
MNU
rw
MSK1
rw
ST
rw
SU
rw
Toggle Fields.

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm B seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm B minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm B hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm B date mask.

WPR

write protection register

Offset: 0x24, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-7: Write protection key.

TSTR

time stamp time register

Offset: 0x30, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
r
HT
r
HU
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
r
MNU
r
ST
r
SU
r
Toggle Fields.

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

TSDR

time stamp date register

Offset: 0x34, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
r
MT
r
MU
r
DT
r
DU
r
Toggle Fields.

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

TAFCR

tamper and alternate function configuration register

Offset: 0x40, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALARMOUTTYPE
rw
TSINSEL
rw
TAMP1INSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMPIE
rw
TAMP1TRG
rw
TAMP1E
rw
Toggle Fields.

TAMP1E

Bit 0: Tamper 1 detection enable.

TAMP1TRG

Bit 1: Active level for tamper 1.

TAMPIE

Bit 2: Tamper interrupt enable.

TAMP1INSEL

Bit 16: TAMPER1 mapping.

TSINSEL

Bit 17: TIMESTAMP mapping.

ALARMOUTTYPE

Bit 18: AFO_ALARM output type.

BKP%sR

backup register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

SCB

0xE000ED00: System control block

5/74 fields covered. Toggle Registers.

CPUID

CPUID base register

Offset: 0x0, reset: 0x410FC241, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Implementer
r
Variant
r
Constant
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PartNo
r
Revision
r
Toggle Fields.

Revision

Bits 0-3: Revision number.

PartNo

Bits 4-15: Part number of the processor.

Constant

Bits 16-19: Reads as 0xF.

Variant

Bits 20-23: Variant number.

Implementer

Bits 24-31: Implementer code.

ICSR

Interrupt control and state register

Offset: 0x4, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NMIPENDSET
rw
PENDSVSET
rw
PENDSVCLR
rw
PENDSTSET
rw
PENDSTCLR
rw
ISRPENDING
rw
VECTPENDING
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VECTPENDING
rw
RETTOBASE
rw
VECTACTIVE
rw
Toggle Fields.

VECTACTIVE

Bits 0-8: Active vector.

RETTOBASE

Bit 11: Return to base level.

VECTPENDING

Bits 12-18: Pending vector.

ISRPENDING

Bit 22: Interrupt pending flag.

PENDSTCLR

Bit 25: SysTick exception clear-pending bit.

PENDSTSET

Bit 26: SysTick exception set-pending bit.

PENDSVCLR

Bit 27: PendSV clear-pending bit.

PENDSVSET

Bit 28: PendSV set-pending bit.

NMIPENDSET

Bit 31: NMI set-pending bit..

VTOR

Vector table offset register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TBLOFF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBLOFF
rw
Toggle Fields.

TBLOFF

Bits 9-29: Vector table base offset field.

AIRCR

Application interrupt and reset control register

Offset: 0xC, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VECTKEYSTAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDIANESS
rw
PRIGROUP
rw
SYSRESETREQ
rw
VECTCLRACTIVE
rw
VECTRESET
rw
Toggle Fields.

VECTRESET

Bit 0: VECTRESET.

VECTCLRACTIVE

Bit 1: VECTCLRACTIVE.

SYSRESETREQ

Bit 2: SYSRESETREQ.

PRIGROUP

Bits 8-10: PRIGROUP.

ENDIANESS

Bit 15: ENDIANESS.

VECTKEYSTAT

Bits 16-31: Register key.

SCR

System control register

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEVEONPEND
rw
SLEEPDEEP
rw
SLEEPONEXIT
rw
Toggle Fields.

SLEEPONEXIT

Bit 1: SLEEPONEXIT.

SLEEPDEEP

Bit 2: SLEEPDEEP.

SEVEONPEND

Bit 4: Send Event on Pending bit.

CCR

Configuration and control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STKALIGN
rw
BFHFNMIGN
rw
DIV_0_TRP
rw
UNALIGN__TRP
rw
USERSETMPEND
rw
NONBASETHRDENA
rw
Toggle Fields.

NONBASETHRDENA

Bit 0: Configures how the processor enters Thread mode.

USERSETMPEND

Bit 1: USERSETMPEND.

UNALIGN__TRP

Bit 3: UNALIGN_ TRP.

DIV_0_TRP

Bit 4: DIV_0_TRP.

BFHFNMIGN

Bit 8: BFHFNMIGN.

STKALIGN

Bit 9: STKALIGN.

SHPR1

System handler priority registers

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_5
rw
PRI_4
rw
Toggle Fields.

PRI_4

Bits 0-7: Priority of system handler 4.

PRI_5

Bits 8-15: Priority of system handler 5.

PRI_6

Bits 16-23: Priority of system handler 6.

SHPR2

System handler priority registers

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_11
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PRI_11

Bits 24-31: Priority of system handler 11.

SHPR3

System handler priority registers

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_15
rw
PRI_14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PRI_14

Bits 16-23: Priority of system handler 14.

PRI_15

Bits 24-31: Priority of system handler 15.

SHCRS

System handler control and state register

Offset: 0x24, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USGFAULTENA
rw
BUSFAULTENA
rw
MEMFAULTENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SVCALLPENDED
rw
BUSFAULTPENDED
rw
MEMFAULTPENDED
rw
USGFAULTPENDED
rw
SYSTICKACT
rw
PENDSVACT
rw
MONITORACT
rw
SVCALLACT
rw
USGFAULTACT
rw
BUSFAULTACT
rw
MEMFAULTACT
rw
Toggle Fields.

MEMFAULTACT

Bit 0: Memory management fault exception active bit.

BUSFAULTACT

Bit 1: Bus fault exception active bit.

USGFAULTACT

Bit 3: Usage fault exception active bit.

SVCALLACT

Bit 7: SVC call active bit.

MONITORACT

Bit 8: Debug monitor active bit.

PENDSVACT

Bit 10: PendSV exception active bit.

SYSTICKACT

Bit 11: SysTick exception active bit.

USGFAULTPENDED

Bit 12: Usage fault exception pending bit.

MEMFAULTPENDED

Bit 13: Memory management fault exception pending bit.

BUSFAULTPENDED

Bit 14: Bus fault exception pending bit.

SVCALLPENDED

Bit 15: SVC call pending bit.

MEMFAULTENA

Bit 16: Memory management fault enable bit.

BUSFAULTENA

Bit 17: Bus fault enable bit.

USGFAULTENA

Bit 18: Usage fault enable bit.

CFSR_UFSR_BFSR_MMFSR

Configurable fault status register

Offset: 0x28, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVBYZERO
rw
UNALIGNED
rw
NOCP
rw
INVPC
rw
INVSTATE
rw
UNDEFINSTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BFARVALID
rw
LSPERR
rw
STKERR
rw
UNSTKERR
rw
IMPRECISERR
rw
PRECISERR
rw
IBUSERR
rw
MMARVALID
rw
MLSPERR
rw
MSTKERR
rw
MUNSTKERR
rw
DACCVIOL
rw
IACCVIOL
rw
Toggle Fields.

IACCVIOL

Bit 0: IACCVIOL.

DACCVIOL

Bit 1: DACCVIOL.

MUNSTKERR

Bit 3: MUNSTKERR.

MSTKERR

Bit 4: MSTKERR.

MLSPERR

Bit 5: MLSPERR.

MMARVALID

Bit 7: MMARVALID.

IBUSERR

Bit 8: Instruction bus error.

PRECISERR

Bit 9: Precise data bus error.

IMPRECISERR

Bit 10: Imprecise data bus error.

UNSTKERR

Bit 11: Bus fault on unstacking for a return from exception.

STKERR

Bit 12: Bus fault on stacking for exception entry.

LSPERR

Bit 13: Bus fault on floating-point lazy state preservation.

BFARVALID

Bit 15: Bus Fault Address Register (BFAR) valid flag.

UNDEFINSTR

Bit 16: Undefined instruction usage fault.

INVSTATE

Bit 17: Invalid state usage fault.

INVPC

Bit 18: Invalid PC load usage fault.

NOCP

Bit 19: No coprocessor usage fault..

UNALIGNED

Bit 24: Unaligned access usage fault.

DIVBYZERO

Bit 25: Divide by zero usage fault.

HFSR

Hard fault status register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEBUG_VT
rw
FORCED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VECTTBL
rw
Toggle Fields.

VECTTBL

Bit 1: Vector table hard fault.

FORCED

Bit 30: Forced hard fault.

DEBUG_VT

Bit 31: Reserved for Debug use.

MMFAR

Memory management fault address register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMFAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMFAR
rw
Toggle Fields.

MMFAR

Bits 0-31: Memory management fault address.

BFAR

Bus fault address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BFAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BFAR
rw
Toggle Fields.

BFAR

Bits 0-31: Bus fault address.

SCB_ACTRL

0xE000E008: System control block ACTLR

0/4 fields covered. Toggle Registers.

ACTRL

Auxiliary control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISITMATBFLUSH
rw
DISRAMODE
rw
FPEXCODIS
rw
DISFOLD
rw
Toggle Fields.

DISFOLD

Bit 2: DISFOLD.

FPEXCODIS

Bit 10: FPEXCODIS.

DISRAMODE

Bit 11: DISRAMODE.

DISITMATBFLUSH

Bit 12: DISITMATBFLUSH.

SDIO

0x40012C00: Secure digital input/output interface

31/98 fields covered. Toggle Registers.

POWER

power control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWRCTRL
rw
Toggle Fields.

PWRCTRL

Bits 0-1: PWRCTRL.

CLKCR

SDI clock control register

Offset: 0x4, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HWFC_EN
rw
NEGEDGE
rw
WIDBUS
rw
BYPASS
rw
PWRSAV
rw
CLKEN
rw
CLKDIV
rw
Toggle Fields.

CLKDIV

Bits 0-7: Clock divide factor.

CLKEN

Bit 8: Clock enable bit.

PWRSAV

Bit 9: Power saving configuration bit.

BYPASS

Bit 10: Clock divider bypass enable bit.

WIDBUS

Bits 11-12: Wide bus mode enable bit.

NEGEDGE

Bit 13: SDIO_CK dephasing selection bit.

HWFC_EN

Bit 14: HW Flow Control enable.

ARG

argument register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDARG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDARG
rw
Toggle Fields.

CMDARG

Bits 0-31: Command argument.

CMD

command register

Offset: 0xC, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CE_ATACMD
rw
nIEN
rw
ENCMDcompl
rw
SDIOSuspend
rw
CPSMEN
rw
WAITPEND
rw
WAITINT
rw
WAITRESP
rw
CMDINDEX
rw
Toggle Fields.

CMDINDEX

Bits 0-5: Command index.

WAITRESP

Bits 6-7: Wait for response bits.

WAITINT

Bit 8: CPSM waits for interrupt request.

WAITPEND

Bit 9: CPSM Waits for ends of data transfer (CmdPend internal signal)..

CPSMEN

Bit 10: Command path state machine (CPSM) Enable bit.

SDIOSuspend

Bit 11: SD I/O suspend command.

ENCMDcompl

Bit 12: Enable CMD completion.

nIEN

Bit 13: not Interrupt Enable.

CE_ATACMD

Bit 14: CE-ATA command.

RESPCMD

command response register

Offset: 0x10, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESPCMD
r
Toggle Fields.

RESPCMD

Bits 0-5: Response command index.

RESP1

response 1..4 register

Offset: 0x14, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS1
r
Toggle Fields.

CARDSTATUS1

Bits 0-31: see Table 132..

RESP2

response 1..4 register

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS2
r
Toggle Fields.

CARDSTATUS2

Bits 0-31: see Table 132..

RESP3

response 1..4 register

Offset: 0x1C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS3
r
Toggle Fields.

CARDSTATUS3

Bits 0-31: see Table 132..

RESP4

response 1..4 register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS4
r
Toggle Fields.

CARDSTATUS4

Bits 0-31: see Table 132..

DTIMER

data timer register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATIME
rw
Toggle Fields.

DATATIME

Bits 0-31: Data timeout period.

DLEN

data length register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALENGTH
rw
Toggle Fields.

DATALENGTH

Bits 0-24: Data length value.

DCTRL

data control register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDIOEN
rw
RWMOD
rw
RWSTOP
rw
RWSTART
rw
DBLOCKSIZE
rw
DMAEN
rw
DTMODE
rw
DTDIR
rw
DTEN
rw
Toggle Fields.

DTEN

Bit 0: DTEN.

DTDIR

Bit 1: Data transfer direction selection.

DTMODE

Bit 2: Data transfer mode selection 1: Stream or SDIO multibyte data transfer..

DMAEN

Bit 3: DMA enable bit.

DBLOCKSIZE

Bits 4-7: Data block size.

RWSTART

Bit 8: Read wait start.

RWSTOP

Bit 9: Read wait stop.

RWMOD

Bit 10: Read wait mode.

SDIOEN

Bit 11: SD I/O enable functions.

DCOUNT

data counter register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACOUNT
r
Toggle Fields.

DATACOUNT

Bits 0-24: Data count value.

STA

status register

Offset: 0x34, reset: 0x00000000, access: read-only

24/24 fields covered.

CCRCFAIL

Bit 0: Command response received (CRC check failed).

DCRCFAIL

Bit 1: Data block sent/received (CRC check failed).

CTIMEOUT

Bit 2: Command response timeout.

DTIMEOUT

Bit 3: Data timeout.

TXUNDERR

Bit 4: Transmit FIFO underrun error.

RXOVERR

Bit 5: Received FIFO overrun error.

CMDREND

Bit 6: Command response received (CRC check passed).

CMDSENT

Bit 7: Command sent (no response required).

DATAEND

Bit 8: Data end (data counter, SDIDCOUNT, is zero).

STBITERR

Bit 9: Start bit not detected on all data signals in wide bus mode.

DBCKEND

Bit 10: Data block sent/received (CRC check passed).

CMDACT

Bit 11: Command transfer in progress.

TXACT

Bit 12: Data transmit in progress.

RXACT

Bit 13: Data receive in progress.

TXFIFOHE

Bit 14: Transmit FIFO half empty: at least 8 words can be written into the FIFO.

RXFIFOHF

Bit 15: Receive FIFO half full: there are at least 8 words in the FIFO.

TXFIFOF

Bit 16: Transmit FIFO full.

RXFIFOF

Bit 17: Receive FIFO full.

TXFIFOE

Bit 18: Transmit FIFO empty.

RXFIFOE

Bit 19: Receive FIFO empty.

TXDAVL

Bit 20: Data available in transmit FIFO.

RXDAVL

Bit 21: Data available in receive FIFO.

SDIOIT

Bit 22: SDIO interrupt received.

CEATAEND

Bit 23: CE-ATA command completion signal received for CMD61.

ICR

interrupt clear register

Offset: 0x38, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEATAENDC
rw
SDIOITC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBCKENDC
rw
STBITERRC
rw
DATAENDC
rw
CMDSENTC
rw
CMDRENDC
rw
RXOVERRC
rw
TXUNDERRC
rw
DTIMEOUTC
rw
CTIMEOUTC
rw
DCRCFAILC
rw
CCRCFAILC
rw
Toggle Fields.

CCRCFAILC

Bit 0: CCRCFAIL flag clear bit.

DCRCFAILC

Bit 1: DCRCFAIL flag clear bit.

CTIMEOUTC

Bit 2: CTIMEOUT flag clear bit.

DTIMEOUTC

Bit 3: DTIMEOUT flag clear bit.

TXUNDERRC

Bit 4: TXUNDERR flag clear bit.

RXOVERRC

Bit 5: RXOVERR flag clear bit.

CMDRENDC

Bit 6: CMDREND flag clear bit.

CMDSENTC

Bit 7: CMDSENT flag clear bit.

DATAENDC

Bit 8: DATAEND flag clear bit.

STBITERRC

Bit 9: STBITERR flag clear bit.

DBCKENDC

Bit 10: DBCKEND flag clear bit.

SDIOITC

Bit 22: SDIOIT flag clear bit.

CEATAENDC

Bit 23: CEATAEND flag clear bit.

MASK

mask register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/24 fields covered.

CCRCFAILIE

Bit 0: Command CRC fail interrupt enable.

DCRCFAILIE

Bit 1: Data CRC fail interrupt enable.

CTIMEOUTIE

Bit 2: Command timeout interrupt enable.

DTIMEOUTIE

Bit 3: Data timeout interrupt enable.

TXUNDERRIE

Bit 4: Tx FIFO underrun error interrupt enable.

RXOVERRIE

Bit 5: Rx FIFO overrun error interrupt enable.

CMDRENDIE

Bit 6: Command response received interrupt enable.

CMDSENTIE

Bit 7: Command sent interrupt enable.

DATAENDIE

Bit 8: Data end interrupt enable.

STBITERRIE

Bit 9: Start bit error interrupt enable.

DBCKENDIE

Bit 10: Data block end interrupt enable.

CMDACTIE

Bit 11: Command acting interrupt enable.

TXACTIE

Bit 12: Data transmit acting interrupt enable.

RXACTIE

Bit 13: Data receive acting interrupt enable.

TXFIFOHEIE

Bit 14: Tx FIFO half empty interrupt enable.

RXFIFOHFIE

Bit 15: Rx FIFO half full interrupt enable.

TXFIFOFIE

Bit 16: Tx FIFO full interrupt enable.

RXFIFOFIE

Bit 17: Rx FIFO full interrupt enable.

TXFIFOEIE

Bit 18: Tx FIFO empty interrupt enable.

RXFIFOEIE

Bit 19: Rx FIFO empty interrupt enable.

TXDAVLIE

Bit 20: Data available in Tx FIFO interrupt enable.

RXDAVLIE

Bit 21: Data available in Rx FIFO interrupt enable.

SDIOITIE

Bit 22: SDIO mode interrupt received interrupt enable.

CEATAENDIE

Bit 23: CE-ATA command completion signal received interrupt enable.

FIFOCNT

FIFO counter register

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOCOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCOUNT
r
Toggle Fields.

FIFOCOUNT

Bits 0-23: Remaining number of words to be written to or read from the FIFO..

FIFO

data FIFO register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOData
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOData
rw
Toggle Fields.

FIFOData

Bits 0-31: Receive and transmit FIFO data.

SPI1

0x40013000: Serial peripheral interface

45/45 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw
BIDIOE
rw
CRCEN
rw
CRCNEXT
rw
DFF
rw
RXONLY
rw
SSM
rw
SSI
rw
LSBFIRST
rw
SPE
rw
BR
rw
MSTR
rw
CPOL
rw
CPHA
rw
Toggle Fields.

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEIE
rw
RXNEIE
rw
ERRIE
rw
FRF
rw
SSOE
rw
TXDMAEN
rw
RXDMAEN
rw
Toggle Fields.

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIFRFE
r
BSY
r
OVR
r
MODF
r
CRCERR
rw
UDR
r
CHSIDE
r
TXE
r
RXNE
r
Toggle Fields.

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

TIFRFE

Bit 8: TI frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

DR

data register

Offset: 0xC, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-15: Data register.

Allowed values: 0-65535

CRCPR

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0-65535

RXCRCR

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle Fields.

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0-65535

TXCRCR

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle Fields.

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0-65535

I2SCFGR

I2S configuration register

Offset: 0x1C, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw
I2SE
rw
I2SCFG
rw
PCMSYNC
rw
I2SSTD
rw
CKPOL
rw
DATLEN
rw
CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, reset: 00000010, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw
ODD
rw
I2SDIV
rw
Toggle Fields.

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 2-255

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SPI2

0x40003800: Serial peripheral interface

45/45 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw
BIDIOE
rw
CRCEN
rw
CRCNEXT
rw
DFF
rw
RXONLY
rw
SSM
rw
SSI
rw
LSBFIRST
rw
SPE
rw
BR
rw
MSTR
rw
CPOL
rw
CPHA
rw
Toggle Fields.

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEIE
rw
RXNEIE
rw
ERRIE
rw
FRF
rw
SSOE
rw
TXDMAEN
rw
RXDMAEN
rw
Toggle Fields.

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIFRFE
r
BSY
r
OVR
r
MODF
r
CRCERR
rw
UDR
r
CHSIDE
r
TXE
r
RXNE
r
Toggle Fields.

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

TIFRFE

Bit 8: TI frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

DR

data register

Offset: 0xC, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-15: Data register.

Allowed values: 0-65535

CRCPR

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0-65535

RXCRCR

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle Fields.

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0-65535

TXCRCR

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle Fields.

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0-65535

I2SCFGR

I2S configuration register

Offset: 0x1C, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw
I2SE
rw
I2SCFG
rw
PCMSYNC
rw
I2SSTD
rw
CKPOL
rw
DATLEN
rw
CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, reset: 00000010, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw
ODD
rw
I2SDIV
rw
Toggle Fields.

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 2-255

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SPI3

0x40003C00: Serial peripheral interface

45/45 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw
BIDIOE
rw
CRCEN
rw
CRCNEXT
rw
DFF
rw
RXONLY
rw
SSM
rw
SSI
rw
LSBFIRST
rw
SPE
rw
BR
rw
MSTR
rw
CPOL
rw
CPHA
rw
Toggle Fields.

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

DFF

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEIE
rw
RXNEIE
rw
ERRIE
rw
FRF
rw
SSOE
rw
TXDMAEN
rw
RXDMAEN
rw
Toggle Fields.

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

FRF

Bit 4: Frame format.

Allowed values:
0: Motorola: SPI Motorola mode
1: TI: SPI TI mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

SR

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIFRFE
r
BSY
r
OVR
r
MODF
r
CRCERR
rw
UDR
r
CHSIDE
r
TXE
r
RXNE
r
Toggle Fields.

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CHSIDE

Bit 2: Channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

UDR

Bit 3: Underrun flag.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

TIFRFE

Bit 8: TI frame format error.

Allowed values:
0: NoError: No frame format error
1: Error: A frame format error occurred

DR

data register

Offset: 0xC, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-15: Data register.

Allowed values: 0-65535

CRCPR

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0-65535

RXCRCR

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle Fields.

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0-65535

TXCRCR

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle Fields.

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0-65535

I2SCFGR

I2S configuration register

Offset: 0x1C, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SMOD
rw
I2SE
rw
I2SCFG
rw
PCMSYNC
rw
I2SSTD
rw
CKPOL
rw
DATLEN
rw
CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DATLEN

Bits 1-2: Data length to be transferred.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPOL

Bit 3: Steady state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSYNC

Bit 7: PCM frame synchronization.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SCFG

Bits 8-9: I2S configuration mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SE

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SMOD

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPR

I2S prescaler register

Offset: 0x20, reset: 00000010, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOE
rw
ODD
rw
I2SDIV
rw
Toggle Fields.

I2SDIV

Bits 0-7: I2S Linear prescaler.

Allowed values: 2-255

ODD

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is I2SDIV * 2
1: Odd: Real divider value is (I2SDIV * 2) + 1

MCKOE

Bit 9: Master clock output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

STK

0xE000E010: SysTick timer

0/7 fields covered. Toggle Registers.

CTRL

SysTick control and status register

Offset: 0x0, reset: 0X00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNTFLAG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKSOURCE
rw
TICKINT
rw
ENABLE
rw
Toggle Fields.

ENABLE

Bit 0: Counter enable.

TICKINT

Bit 1: SysTick exception request enable.

CLKSOURCE

Bit 2: Clock source selection.

COUNTFLAG

Bit 16: COUNTFLAG.

LOAD_

SysTick reload value register

Offset: 0x4, reset: 0X00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RELOAD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD
rw
Toggle Fields.

RELOAD

Bits 0-23: RELOAD value.

VAL

SysTick current value register

Offset: 0x8, reset: 0X00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURRENT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRENT
rw
Toggle Fields.

CURRENT

Bits 0-23: Current counter value.

CALIB

SysTick calibration value register

Offset: 0xC, reset: 0X00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TENMS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TENMS
rw
Toggle Fields.

TENMS

Bits 0-23: Calibration value.

SYSCFG

0x40013800: System configuration controller

1/20 fields covered. Toggle Registers.

MEMRM

memory remap register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM_MODE
rw
Toggle Fields.

MEM_MODE

Bits 0-1: MEM_MODE.

PMC

peripheral mode configuration register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MII_RMII_SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

MII_RMII_SEL

Bit 23: Ethernet PHY interface selection.

EXTICR1

external interrupt configuration register 1

Offset: 0x8, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3
rw
EXTI2
rw
EXTI1
rw
EXTI0
rw
Toggle Fields.

EXTI0

Bits 0-3: EXTI x configuration (x = 0 to 3).

EXTI1

Bits 4-7: EXTI x configuration (x = 0 to 3).

EXTI2

Bits 8-11: EXTI x configuration (x = 0 to 3).

EXTI3

Bits 12-15: EXTI x configuration (x = 0 to 3).

EXTICR2

external interrupt configuration register 2

Offset: 0xC, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7
rw
EXTI6
rw
EXTI5
rw
EXTI4
rw
Toggle Fields.

EXTI4

Bits 0-3: EXTI x configuration (x = 4 to 7).

EXTI5

Bits 4-7: EXTI x configuration (x = 4 to 7).

EXTI6

Bits 8-11: EXTI x configuration (x = 4 to 7).

EXTI7

Bits 12-15: EXTI x configuration (x = 4 to 7).

EXTICR3

external interrupt configuration register 3

Offset: 0x10, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11
rw
EXTI10
rw
EXTI9
rw
EXTI8
rw
Toggle Fields.

EXTI8

Bits 0-3: EXTI x configuration (x = 8 to 11).

EXTI9

Bits 4-7: EXTI x configuration (x = 8 to 11).

EXTI10

Bits 8-11: EXTI10.

EXTI11

Bits 12-15: EXTI x configuration (x = 8 to 11).

EXTICR4

external interrupt configuration register 4

Offset: 0x14, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15
rw
EXTI14
rw
EXTI13
rw
EXTI12
rw
Toggle Fields.

EXTI12

Bits 0-3: EXTI x configuration (x = 12 to 15).

EXTI13

Bits 4-7: EXTI x configuration (x = 12 to 15).

EXTI14

Bits 8-11: EXTI x configuration (x = 12 to 15).

EXTI15

Bits 12-15: EXTI x configuration (x = 12 to 15).

CMPCR

Compensation cell control register

Offset: 0x20, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READY
r
CMP_PD
rw
Toggle Fields.

CMP_PD

Bit 0: Compensation cell power-down.

READY

Bit 7: READY.

TIM1

0x40010000: Advanced-timers

77/124 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

3/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw
OIS3N
rw
OIS3
rw
OIS2N
rw
OIS2
rw
OIS1N
rw
OIS1
rw
TI1S
rw
MMS
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle Fields.

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
COMDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
BIE
rw
TIE
rw
COMIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

10/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
BIF
rw
TIF
rw
COMIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
TG
w
COMG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC2G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC3G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC4G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

Allowed values: 0-15

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC3PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0-3

IC3F

Bits 4-7: Input capture 3 filter.

Allowed values: 0-15

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC4PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0-3

IC4F

Bits 12-15: Input capture 4 filter.

Allowed values: 0-15

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4P
rw
CC4E
rw
CC3NP
rw
CC3NE
rw
CC3P
rw
CC3E
rw
CC2NP
rw
CC2NE
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1NE
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0-65535

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields.

REP

Bits 0-7: Repetition counter value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

Allowed values: 0-65535

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

3/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle Fields.

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

Allowed values: 0-31

DBL

Bits 8-12: DMA burst length.

Allowed values: 0-18

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

TIM10

0x40014400: General-purpose-timers

9/27 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

OR

option register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMP
rw
Toggle Fields.

RMP

Bits 0-1: Input 1 remapping capability.

TIM11

0x40014800: General-purpose-timers

9/27 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

OR

option register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMP
rw
Toggle Fields.

RMP

Bits 0-1: Input 1 remapping capability.

TIM12

0x40001800: General-purpose-timers

10/48 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields.

MMS

Bits 4-6: Master mode selection.

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2OF
rw
CC1OF
rw
TIF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-6: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-14: Input capture 2 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2NP
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

TIM13

0x40001C00: General-purpose-timers

9/27 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

OR

option register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMP
rw
Toggle Fields.

RMP

Bits 0-1: Input 1 remapping capability.

TIM14

0x40002000: General-purpose-timers

9/27 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation.

CCMR1_Input

capture/compare mode register (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

OR

option register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMP
rw
Toggle Fields.

RMP

Bits 0-1: Input 1 remapping capability.

TIM2

0x40000000: General-purpose-timers

74/98 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle Fields.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
TIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
TIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC2G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC3G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC4G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

Allowed values: 0-15

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC3PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0-3

IC3F

Bits 4-7: Input capture 3 filter.

Allowed values: 0-15

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC4PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0-3

IC4F

Bits 12-15: Input capture 4 filter.

Allowed values: 0-15

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw
CC4P
rw
CC4E
rw
CC3NP
rw
CC3P
rw
CC3E
rw
CC2NP
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-31: Counter value.

Allowed values: 0-4294967295

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-31: Auto-reload value.

Allowed values: 0-4294967295

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-31: Capture/Compare 1 value.

Allowed values: 0-4294967295

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

Allowed values: 0-31

DBL

Bits 8-12: DMA burst length.

Allowed values: 0-18

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

TIM2_OR

TIM2 option register

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IT4_RMP
rw
Toggle Fields.

IT4_RMP

Bits 6-7: Timer Input 4 remap.

TIM3

0x40000400: General-purpose-timers

74/100 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle Fields.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
TIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
TIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC2G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC3G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC4G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

Allowed values: 0-15

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC3PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0-3

IC3F

Bits 4-7: Input capture 3 filter.

Allowed values: 0-15

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC4PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0-3

IC4F

Bits 12-15: Input capture 4 filter.

Allowed values: 0-15

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw
CC4P
rw
CC4E
rw
CC3NP
rw
CC3P
rw
CC3E
rw
CC2NP
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Counter value.

Allowed values: 0-65535

CNT_H

Bits 16-31: High counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0-65535

ARR_H

Bits 16-31: High Auto-reload value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

Allowed values: 0-65535

CCR1_H

Bits 16-31: High Capture/Compare 1 value.

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

Allowed values: 0-31

DBL

Bits 8-12: DMA burst length.

Allowed values: 0-18

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

TIM4

0x40000800: General-purpose-timers

74/100 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle Fields.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
TIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
TIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC2G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC3G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC4G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

Allowed values: 0-15

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC3PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0-3

IC3F

Bits 4-7: Input capture 3 filter.

Allowed values: 0-15

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC4PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0-3

IC4F

Bits 12-15: Input capture 4 filter.

Allowed values: 0-15

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw
CC4P
rw
CC4E
rw
CC3NP
rw
CC3P
rw
CC3E
rw
CC2NP
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Counter value.

Allowed values: 0-65535

CNT_H

Bits 16-31: High counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0-65535

ARR_H

Bits 16-31: High Auto-reload value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

Allowed values: 0-65535

CCR1_H

Bits 16-31: High Capture/Compare 1 value.

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

Allowed values: 0-31

DBL

Bits 8-12: DMA burst length.

Allowed values: 0-18

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

TIM5

0x40000C00: General-purpose-timers

74/98 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle Fields.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
TIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
TIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC2G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC3G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC4G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

Allowed values: 0-15

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC3PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0-3

IC3F

Bits 4-7: Input capture 3 filter.

Allowed values: 0-15

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC4PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0-3

IC4F

Bits 12-15: Input capture 4 filter.

Allowed values: 0-15

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw
CC4P
rw
CC4E
rw
CC3NP
rw
CC3P
rw
CC3E
rw
CC2NP
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-31: Counter value.

Allowed values: 0-4294967295

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-31: Auto-reload value.

Allowed values: 0-4294967295

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-31: Capture/Compare 1 value.

Allowed values: 0-4294967295

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

Allowed values: 0-31

DBL

Bits 8-12: DMA burst length.

Allowed values: 0-18

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

TIM5_OR

TIM5 option register

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IT4_RMP
rw
Toggle Fields.

IT4_RMP

Bits 6-7: Timer Input 4 remap.

TIM6

0x40001000: Basic-timers

13/13 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields.

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Low counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Low Auto-reload value.

Allowed values: 0-65535

TIM7

0x40001400: Basic-timers

13/13 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields.

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Low counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Low Auto-reload value.

Allowed values: 0-65535

TIM8

0x40010400: Advanced-timers

77/124 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

3/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw
OIS3N
rw
OIS3
rw
OIS2N
rw
OIS2
rw
OIS1N
rw
OIS1
rw
TI1S
rw
MMS
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle Fields.

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
COMDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
BIE
rw
TIE
rw
COMIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

10/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
BIF
rw
TIF
rw
COMIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
TG
w
COMG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC2G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC3G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC4G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

Allowed values: 0-15

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC3PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0-3

IC3F

Bits 4-7: Input capture 3 filter.

Allowed values: 0-15

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC4PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0-3

IC4F

Bits 12-15: Input capture 4 filter.

Allowed values: 0-15

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4P
rw
CC4E
rw
CC3NP
rw
CC3NE
rw
CC3P
rw
CC3E
rw
CC2NP
rw
CC2NE
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1NE
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0-65535

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields.

REP

Bits 0-7: Repetition counter value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

Allowed values: 0-65535

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

3/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle Fields.

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

Allowed values: 0-31

DBL

Bits 8-12: DMA burst length.

Allowed values: 0-18

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

TIM9

0x40014000: General-purpose-timers

10/48 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields.

MMS

Bits 4-6: Master mode selection.

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2OF
rw
CC1OF
rw
TIF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-6: Input capture 1 filter.

CC2S

Bits 8-9: Capture/Compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-14: Input capture 2 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2NP
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

UART4

0x40004C00: Universal synchronous asynchronous receiver transmitter

36/39 fields covered. Toggle Registers.

SR

Status register

Offset: 0x0, reset: 0x00C0, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LBD
rw
TXE
r
TC
rw
RXNE
rw
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

DR

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-8: Data value.

Allowed values: 0-511

BRR

Baud rate register

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw
DIV_Fraction
rw
Toggle Fields.

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

Allowed values: 0-15

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

Allowed values: 0-4095

CR1

Control register 1

Offset: 0xC, reset: 0x0000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
UE
rw
M
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
RWU
rw
SBK
rw
Toggle Fields.

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversample16: Oversampling by 16
1: Oversample8: Oversampling by 8

CR2

Control register 2

Offset: 0x10, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw
STOP
rw
LBDIE
rw
LBDL
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0-15

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
2: Stop2: 2 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

Control register 3

Offset: 0x14, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw
DMAT
rw
DMAR
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

UART5

0x40005000: Universal synchronous asynchronous receiver transmitter

36/39 fields covered. Toggle Registers.

SR

Status register

Offset: 0x0, reset: 0x00C0, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LBD
rw
TXE
r
TC
rw
RXNE
rw
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

DR

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-8: Data value.

Allowed values: 0-511

BRR

Baud rate register

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw
DIV_Fraction
rw
Toggle Fields.

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

Allowed values: 0-15

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

Allowed values: 0-4095

CR1

Control register 1

Offset: 0xC, reset: 0x0000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
UE
rw
M
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
RWU
rw
SBK
rw
Toggle Fields.

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversample16: Oversampling by 16
1: Oversample8: Oversampling by 8

CR2

Control register 2

Offset: 0x10, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw
STOP
rw
LBDIE
rw
LBDL
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0-15

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
2: Stop2: 2 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

Control register 3

Offset: 0x14, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw
DMAT
rw
DMAR
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

USART1

0x40011000: Universal synchronous asynchronous receiver transmitter

44/51 fields covered. Toggle Registers.

SR

Status register

Offset: 0x0, reset: 0x00C0, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw
LBD
rw
TXE
r
TC
rw
RXNE
rw
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-8: Data value.

Allowed values: 0-511

BRR

Baud rate register

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw
DIV_Fraction
rw
Toggle Fields.

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

Allowed values: 0-15

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

Allowed values: 0-4095

CR1

Control register 1

Offset: 0xC, reset: 0x0000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
UE
rw
M
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
RWU
rw
SBK
rw
Toggle Fields.

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversample16: Oversampling by 16
1: Oversample8: Oversampling by 8

CR2

Control register 2

Offset: 0x10, reset: 0x0000, access: read-write

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0-15

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bits
2: Stop2: 2 stop bits
3: Stop1p5: 1.5 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

Control register 3

Offset: 0x14, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard mode disabled
1: Enabled: Smartcard mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS hardware flow control enabled

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS hardware flow control enabled

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: CTS interrupt disabled
1: Enabled: CTS interrupt enabled

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

GTPR

Guard time and prescaler register

Offset: 0x18, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USART2

0x40004400: Universal synchronous asynchronous receiver transmitter

44/51 fields covered. Toggle Registers.

SR

Status register

Offset: 0x0, reset: 0x00C0, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw
LBD
rw
TXE
r
TC
rw
RXNE
rw
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-8: Data value.

Allowed values: 0-511

BRR

Baud rate register

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw
DIV_Fraction
rw
Toggle Fields.

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

Allowed values: 0-15

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

Allowed values: 0-4095

CR1

Control register 1

Offset: 0xC, reset: 0x0000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
UE
rw
M
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
RWU
rw
SBK
rw
Toggle Fields.

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversample16: Oversampling by 16
1: Oversample8: Oversampling by 8

CR2

Control register 2

Offset: 0x10, reset: 0x0000, access: read-write

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0-15

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bits
2: Stop2: 2 stop bits
3: Stop1p5: 1.5 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

Control register 3

Offset: 0x14, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard mode disabled
1: Enabled: Smartcard mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS hardware flow control enabled

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS hardware flow control enabled

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: CTS interrupt disabled
1: Enabled: CTS interrupt enabled

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

GTPR

Guard time and prescaler register

Offset: 0x18, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USART3

0x40004800: Universal synchronous asynchronous receiver transmitter

44/51 fields covered. Toggle Registers.

SR

Status register

Offset: 0x0, reset: 0x00C0, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw
LBD
rw
TXE
r
TC
rw
RXNE
rw
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-8: Data value.

Allowed values: 0-511

BRR

Baud rate register

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw
DIV_Fraction
rw
Toggle Fields.

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

Allowed values: 0-15

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

Allowed values: 0-4095

CR1

Control register 1

Offset: 0xC, reset: 0x0000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
UE
rw
M
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
RWU
rw
SBK
rw
Toggle Fields.

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversample16: Oversampling by 16
1: Oversample8: Oversampling by 8

CR2

Control register 2

Offset: 0x10, reset: 0x0000, access: read-write

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0-15

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bits
2: Stop2: 2 stop bits
3: Stop1p5: 1.5 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

Control register 3

Offset: 0x14, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard mode disabled
1: Enabled: Smartcard mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS hardware flow control enabled

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS hardware flow control enabled

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: CTS interrupt disabled
1: Enabled: CTS interrupt enabled

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

GTPR

Guard time and prescaler register

Offset: 0x18, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

USART6

0x40011400: Universal synchronous asynchronous receiver transmitter

44/51 fields covered. Toggle Registers.

SR

Status register

Offset: 0x0, reset: 0x00C0, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
rw
LBD
rw
TXE
r
TC
rw
RXNE
rw
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: Parity error.

FE

Bit 1: Framing error.

NF

Bit 2: Noise detected flag.

ORE

Bit 3: Overrun error.

IDLE

Bit 4: IDLE line detected.

RXNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TXE

Bit 7: Transmit data register empty.

LBD

Bit 8: LIN break detection flag.

CTS

Bit 9: CTS flag.

DR

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-8: Data value.

Allowed values: 0-511

BRR

Baud rate register

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV_Mantissa
rw
DIV_Fraction
rw
Toggle Fields.

DIV_Fraction

Bits 0-3: fraction of USARTDIV.

Allowed values: 0-15

DIV_Mantissa

Bits 4-15: mantissa of USARTDIV.

Allowed values: 0-4095

CR1

Control register 1

Offset: 0xC, reset: 0x0000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
UE
rw
M
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
RWU
rw
SBK
rw
Toggle Fields.

SBK

Bit 0: Send break.

Allowed values:
0: NoBreak: No break character is transmitted
1: Break: Break character transmitted

RWU

Bit 1: Receiver wakeup.

Allowed values:
0: Active: Receiver in active mode
1: Mute: Receiver in mute mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver disabled
1: Enabled: Receiver enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter disabled
1: Enabled: Transmitter enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: IDLE interrupt disabled
1: Enabled: IDLE interrupt enabled

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: RXNE interrupt disabled
1: Enabled: RXNE interrupt enabled

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: TC interrupt disabled
1: Enabled: TC interrupt enabled

TXEIE

Bit 7: TXE interrupt enable.

Allowed values:
0: Disabled: TXE interrupt disabled
1: Enabled: TXE interrupt enabled

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: PE interrupt disabled
1: Enabled: PE interrupt enabled

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Wakeup method.

Allowed values:
0: IdleLine: USART wakeup on idle line
1: AddressMark: USART wakeup on address mark

M

Bit 12: Word length.

Allowed values:
0: M8: 8 data bits
1: M9: 9 data bits

UE

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART enabled

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversample16: Oversampling by 16
1: Oversample8: Oversampling by 8

CR2

Control register 2

Offset: 0x10, reset: 0x0000, access: read-write

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-3: Address of the USART node.

Allowed values: 0-15

LBDL

Bit 5: lin break detection length.

Allowed values:
0: LBDL10: 10-bit break detection
1: LBDL11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: LIN break detection interrupt disabled
1: Enabled: LIN break detection interrupt enabled

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bits
2: Stop2: 2 stop bits
3: Stop1p5: 1.5 stop bits

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CR3

Control register 3

Offset: 0x14, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: FullDuplex: Half duplex mode is not selected
1: HalfDuplex: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard mode disabled
1: Enabled: Smartcard mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS hardware flow control enabled

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS hardware flow control enabled

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: CTS interrupt disabled
1: Enabled: CTS interrupt enabled

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

GTPR

Guard time and prescaler register

Offset: 0x18, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

WWDG

0x40002C00: Window watchdog

6/6 fields covered. Toggle Registers.

CR

Control register

Offset: 0x0, reset: 0x7F, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGA
rw
T
rw
Toggle Fields.

T

Bits 0-6: 7-bit counter (MSB to LSB).

Allowed values: 0-127

WDGA

Bit 7: Activation bit.

Allowed values:
0: Disabled: Watchdog disabled
1: Enabled: Watchdog enabled

CFR

Configuration register

Offset: 0x4, reset: 0x7F, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWI
rw
WDGTB
rw
W
rw
Toggle Fields.

W

Bits 0-6: 7-bit window value.

Allowed values: 0-127

WDGTB

Bits 7-8: Timer base.

Allowed values:
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8

EWI

Bit 9: Early wakeup interrupt.

Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40

SR

Status register

Offset: 0x8, reset: 0x00, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle Fields.

EWIF

Bit 0: Early wakeup interrupt flag.

Allowed values:
1: Pending: The EWI Interrupt Service Routine has been triggered
0: Finished: The EWI Interrupt Service Routine has been serviced